Zynq UltraScale+ Quad Ethernet GEM with Shared MDIO

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We're running into issues when attempting to bring up all of our GEMs on our custom UltraScale design. Everytime we attempt to enable the GEMs only one of them bind to the correct PHY and functions. If other PHYs are enabled in the device tree, the wonrg GEM (say GEM0) gets selected even though we clearly have configured the device tree in a fashion where GEM2 should be the MDIO controller.

Our set up is as follows:

-GEM0 (SGMII) -> PHY@2

-GEM1 (SGMII) -> PHY@8

-GEM2 (SGMII) -> PHY@0

-GEM3 (SGMII) -> PHY@1

We've tried the following methods mentioned in previous posts and wiki pages with no success:

https://forums.xilinx.com/t5/Embedded-Linux/Problem-with-Marvell-88E6320-connected-to-GEM3-in-ZynqMP/td-p/902612

https://forums.xilinx.com/t5/Embedded-Linux/dual-PHY-on-single-MDIO-bus-using-xilinx-emacps-c/td-p/727191

https://forums.xilinx.com/t5/Embedded-Linux/Dual-Marvell-88e1512-PHY-Ethernet-problem-Xilinx-LInux/m-p/731207#M17356

https://lists.yoctoproject.org/pipermail/meta-xilinx/2018-February/003686.html

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841740/Macb+Driver

For reference we are using buildroot to compile our kernel. 

What is the official method to enable all GEMs on a shared MDIO bus?

[alindsaybws]

You've probably solved this by now, but I ran into the same problem as you.
The wiki didn't work for me.

I found this official answer from Xilinx:
https://www.xilinx.com/support/answers/69132.html

I managed to use this to make a patch for linux-xlnx version 2019.1 (attached).
Then make sure to add the mdio device, and 'phy-handle' for each gem device in the device tree.
Don't forget to do 'ifup eth1' to bring up the interface once it's all booted.