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Observer tkato@poc.com
Observer
478 Views
Registered: ‎09-06-2019

Zynq Ultrascale Ethernet Bring-up Issue

Hi,

We’re currently trying to bring up a GEM on our custom ultrascale+ board and are facing issues during the initial boot. We’re able to reach u-boot but our ethernet PHYs are not being recognized. The BOOT.bin image is created via Petalinux 2018.3 and .hdf file generated in Vivado 2018.3 on an Ubuntu 16.04 VM.

Our design has all 4 PHYs connected on a single MDIO bus as well.

We've enabled the U-Boot and Ethernet drivers in <PETALINUX PROJ>/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h as such:

/*Enable gpio uboot Drivers*/
#define CONFIG_DM_GPIO
#define CONFIG_ZYNQ_GPIO
#define CONFIG_CMD_GPIO

/*Enable uboot ethernet driver*/
#define CONFIG_ZYNQ_GEM
#define CONFIG_DM_ETH
#define CONFIG_NET_RANDOM_ETHADDR

And modified the <PETALINUX PROJ>/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi to configure the gems with the phy handles and mdio grouping:

/include/ "system-conf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>

/{
};

&gem3 {
	status = "okay";
	phy-handle = <&phy1>;
	phy-mode = "rgmii-id";
};
&gem2 {
	status = "okay";
	phy-handle = <&phy0>;
	phy-mode = "rgmii-id";
	phy0: phy@0 {
		reg = <0x0>;
		ti,rx-internal-delay = <0x8>;
		ti,tx-internal-delay = <0xa>;
		ti,fifo-depth = <0x1>;
		ti,rxctrl-strap-worka;
	};
	phy1: phy@1 {
		reg = <0x1>;
		ti,rx-internal-delay = <0x8>;
		ti,tx-internal-delay = <0xa>;
		ti,fifo-depth = <0x1>;
		ti,rxctrl-strap-worka;
	};
	phy2: phy@2 {
		reg = <0x2>;
	};
	phy8: phy@8 {
		reg = <0x8>;
	};
};
&gem1 {
	status = "disabled";
	phy-handle = <&phy8>;
	phy-mode = "sgmii";
};
&gem0 {
	status = "disabled";
	phy-handle = <&phy2>;
	phy-mode = "sgmii";
};
&qspi {
	status = "okay";
	is-dual = <1>;
	flash@0 {
		compatible = "n25q128a11"; //detected was n25q00a
		reg = <0x0>;
		spi-tx-bus-width = <4>; //was 1
		spi-rx-bus-width = <4>;
		spi-max-frequency = <60000000>; 
		#address-cells = <1>;
		#size-cells = <1>;
		partition@uboot {
			label = "uboot";
			reg = <0x0 0x180000>;
		};
		partition@uenv {
			label = "uenv";
			reg = <0x0180000 0x40000>;
		};
		partition@config {
			label = "config";
			reg = <0x01c0000 0x40000>;
		};/* 2MB upto here */
		partition@bitstream {
			label = "bitstream";
			reg = <0x200000 0x1000000>; //16MB
		};
		partition@kernel1 {
			label = "kernel1";
			reg = <0x1200000 0x5800000>; //8MB + 80MB overlap to rootfs1
		};
		partition@rootfs1 {
			label = "rootfs1";
			reg = <0x1a00000 0x5000000>; //80MB
		};
		partition@kernel2 {
			label = "kernel2";
			reg = <0x6a00000 0x5800000>; //8MB + 80MB overlap to rootfs2
		};
		partition@rootfs2 {
			label = "rootfs2";
			reg = <0x7200000 0x5000000>; //80MB
		};
		partition@sysdiag {
			label = "sysdiag";
			reg = <0xc200000 0x200000>; //2MB
		};
		partition@sys {
			label = "sys";
			reg = <0xc400000 0x0>; //the rest
		};
	};
};

After building the boot image and loading it on the device, our boot screen prints:

ZynqMP> Xilinx Zynq MP First Stage Boot Loader
Release 2018.3   Sep 14 2019  -  20:23:41
NOTICE:  ATF running on XCZU7EV/silicon v4/RTL5.1 at 0xfffea000
NOTICE:  BL31: Secure code at 0x0
NOTICE:  BL31: Non secure code at 0x8000000
NOTICE:  BL31: v1.5(release):xilinx-v2018.2-919-g08560c36
NOTICE:  BL31: Built : 19:42:01, Sep 19 2019
PMUFW:  v1.1


U-Boot 2018.01 (Sep 19 2019 - 23:52:35 +0000) Xilinx ZynqMP ZCU102 rev1.0

I2C:   ready
DRAM:  4 GiB
EL Level:       EL2
Chip ID:        zu7ev
SF: Detected n25q1024a with page size 512 Bytes, erase size 128 KiB, total 256 MiB
*** Warning - bad CRC, using default environment

In:    serial@ff000000
Out:   serial@ff000000
Err:   serial@ff000000
Board: Xilinx ZynqMP
Bootmode: QSPI_MODE
Net:   ZYNQ GEM: ff0d0000, phyaddr 0, interface rgmii-id
PHY is not detected
GEM PHY init failed
No ethernet found.
U-BOOT for dev

ZYNQ GEM: ff0d0000, phyaddr 0, interface rgmii-id
mdio_register: non unique device name 'eth2'
ZYNQ GEM: ff0d0000, phyaddr 0, interface rgmii-id
mdio_register: non unique device name 'eth2'
ZYNQ GEM: ff0d0000, phyaddr 0, interface rgmii-id
mdio_register: non unique device name 'eth2'
ZYNQ GEM: ff0d0000, phyaddr 0, interface rgmii-id
mdio_register: non unique device name 'eth2'
No ethernet found.
ZYNQ GEM: ff0d0000, phyaddr 0, interface rgmii-id
mdio_register: non unique device name 'eth2'
Hit any key to stop autoboot:  0
SF: Detected n25q1024a with page size 512 Bytes, erase size 128 KiB, total 256 MiB
device 0 offset 0x1500000, size 0x1600000
SF: 23068672 bytes @ 0x1500000 Read: OK
Wrong Image Format for bootm command
ERROR: can't get kernel image!
ZynqMP>

As you can see the initialization of the GEM PHY fails due to the PHY not being detected. We have a different project in which the dtsi is set up in a similar manner and the GEM initializes properly. We've used the GPIO driver to toggle the reset to the phy in case the polarity of our pull of was inverted but the phy was still undetected. At this point we are suspicious of our device tree source include file.

Another issue is the error:

ZYNQ GEM: ff0d0000, phyaddr 0, interface rgmii-id
mdio_register: non unique device name 'eth2'

I'm unsure where the device name could be overlapping. Does anyone know where the source of this error could be?

Thanks in advance!

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8 Replies
Adventurer
Adventurer
443 Views
Registered: ‎04-22-2015

Re: Zynq Ultrascale Ethernet Bring-up Issue

Is the address of the PHY through MDIO really 0?
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Observer tkato@poc.com
Observer
427 Views
Registered: ‎09-06-2019

Re: Zynq Ultrascale Ethernet Bring-up Issue

Yes, we have a different image that is able to initialize the phy using address 0x0.
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Moderator
Moderator
340 Views
Registered: ‎12-04-2016

Re: Zynq Ultrascale Ethernet Bring-up Issue

Hi tkato@poc.com 

Can you try to manually apply the attached patch changes for uboot multiple PHY support and see if that helps?

 

Best Regards

Shabbir

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Observer tkato@poc.com
Observer
315 Views
Registered: ‎09-06-2019

Re: Zynq Ultrascale Ethernet Bring-up Issue

Where would the appropriate file be to add this patch? My project doesn't seem to have a recipes-kernel directory. The only existing directories available are recipes-core, recipes-bsp, conf and recipes-apps.

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Visitor lunohod
Visitor
296 Views
Registered: ‎10-12-2018

Re: Zynq Ultrascale Ethernet Bring-up Issue

This patch is for the uboot, add it to recipes-bsp/u-boot.

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Observer tkato@poc.com
Observer
270 Views
Registered: ‎09-06-2019

Re: Zynq Ultrascale Ethernet Bring-up Issue

Ok I've applied the patch and running a build now.

Regarding the GEM configuration in the device tree - is it required to add the following pinctrl_gem3_default node to system-user.dsti? As originally shown here: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842124/U-Boot+Ethernet+Driver

I ask because this seems like redundant information that should have been configured during the GEM configuration within Vivado. Do the pin control settings for the GEMs have be added to the device tree manually? Or is there a mechanism in Petalinux to add the required baseline nodes to the system device tree using information provided by the .hdf? 

&&gem3 {
       status = "okay";
       phy-handle = <&&phy0>;
       phy-mode = "rgmii-id";
       pinctrl-names = "default";
       pinctrl-0 = <&&pinctrl_gem3_default>;
       phy0: phy@21 {
               reg = <21>;
               ti,rx-internal-delay = <0x8>;
               ti,tx-internal-delay = <0xa>;
               ti,fifo-depth = <0x1>;
               ti,rxctrl-strap-worka;
       };
};
  
       pinctrl_gem3_default: gem3-default {
               mux {
                       function = "ethernet3";
                     groups = "ethernet3_0_grp";
               };
  
               conf {
                       groups = "ethernet3_0_grp";
                       slew-rate = <SLEW_RATE_SLOW>;
                       io-standard = <IO_STANDARD_LVCMOS18>;
               };
  
               conf-rx {
                       pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74","MIO75";
                       bias-high-impedance;
                        low-power-disable;
               };
  
               conf-tx {
                       pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68","MIO69";
                       bias-disable;
                       low-power-enable;
               };
  
               mux-mdio {
                       function = "mdio3";
                       groups = "mdio3_0_grp";
               };
  
               conf-mdio {
                       groups = "mdio3_0_grp";
                       slew-rate = <SLEW_RATE_SLOW>;
                       io-standard = <IO_STANDARD_LVCMOS18>;
                       bias-disable;
               };
       };

I've generated the output system.dtb files created by petalinux-build however there is no configuration of GEMs in the pin control.

 

 

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Observer tkato@poc.com
Observer
247 Views
Registered: ‎09-06-2019

Re: Zynq Ultrascale Ethernet Bring-up Issue

After applying the patch I am still having issues with the GEMs coming up. Here is the output log:

Xilinx Zynq MP First Stage Boot Loader
Release 2018.3   Sep 24 2019  -  00:35:33
NOTICE:  ATF running on XCZU7EV/silicon v4/RTL5.1 at 0xfffea000
NOTICE:  BL31: Secure code at 0x0
NOTICE:  BL31: Non secure code at 0x8000000
NOTICE:  BL31: v1.5(release):xilinx-v2018.2-919-g08560c36
NOTICE:  BL31: Built : 00:39:42, Sep 24 2019
PMUFW:  v1.1


U-Boot 2018.01 (Sep 24 2019 - 03:04:18 +0000) Xilinx ZynqMP ZCU102 rev1.0

I2C:   ready
DRAM:  4 GiB
EL Level:       EL2
Chip ID:        zu7ev
SF: Detected n25q1024a with page size 512 Bytes, erase size 128 KiB, total 256 MiB
*** Warning - bad CRC, using default environment

In:    serial@ff000000
Out:   serial@ff000000
Err:   serial@ff000000
Board: Xilinx ZynqMP
Bootmode: QSPI_MODE
Net:   ZYNQ GEM: ff0b0000, mdio bus ff0d0000, phyaddr 2, interface sgmii
Could not get PHY for eth0: addr 2
No ethernet found.
U-BOOT for petalinux

ZYNQ GEM: ff0b0000, mdio bus ff0d0000, phyaddr 2, interface sgmii
mdio_register: non unique device name 'eth0'
ZYNQ GEM: ff0b0000, mdio bus ff0d0000, phyaddr 2, interface sgmii
mdio_register: non unique device name 'eth0'
ZYNQ GEM: ff0b0000, mdio bus ff0d0000, phyaddr 2, interface sgmii
mdio_register: non unique device name 'eth0'
ZYNQ GEM: ff0b0000, mdio bus ff0d0000, phyaddr 2, interface sgmii
mdio_register: non unique device name 'eth0'
No ethernet found.
ZYNQ GEM: ff0b0000, mdio bus ff0d0000, phyaddr 2, interface sgmii
mdio_register: non unique device name 'eth0'
Hit any key to stop autoboot:  0
SF: Detected n25q1024a with page size 512 Bytes, erase size 128 KiB, total 256 MiB
device 0 offset 0x140000, size 0x1600000
SF: 23068672 bytes @ 0x140000 Read: OK
Wrong Image Format for bootm command
ERROR: can't get kernel image!
ZynqMP> gpio
gpio - query and control gpio pins

Usage:
gpio <input|set|clear|toggle> <pin>
    - input/set/clear/toggle the specified pin
gpio status [-a] [<bank> | <pin>]  - show [all/claimed] GPIOs
ZynqMP>

I find that this line in particular seems suspicious:

Net:   ZYNQ GEM: ff0b0000, mdio bus ff0d0000, phyaddr 2, interface sgmii
Could not get PHY for eth0: addr 2
No ethernet found.
U-BOOT for petalinux

It's not clear to me why uboot is now trying to connect Zynq GEM0 rather than GEM2 as it did prior to the build with the latest patch.

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Observer tkato@poc.com
Observer
244 Views
Registered: ‎09-06-2019

Re: Zynq Ultrascale Ethernet Bring-up Issue

Here is the ouput following the application of the patch. It's still having issues and is now attempting to connect to eth0:

 

Xilinx Zynq MP First Stage Boot Loader
Release 2018.3   Sep 24 2019  -  00:35:33
NOTICE:  ATF running on XCZU7EV/silicon v4/RTL5.1 at 0xfffea000
NOTICE:  BL31: Secure code at 0x0
NOTICE:  BL31: Non secure code at 0x8000000
NOTICE:  BL31: v1.5(release):xilinx-v2018.2-919-g08560c36
NOTICE:  BL31: Built : 00:39:42, Sep 24 2019
PMUFW:  v1.1


U-Boot 2018.01 (Sep 24 2019 - 03:04:18 +0000) Xilinx ZynqMP ZCU102 rev1.0

I2C:   ready
DRAM:  4 GiB
EL Level:       EL2
Chip ID:        zu7ev
SF: Detected n25q1024a with page size 512 Bytes, erase size 128 KiB, total 256 MiB
*** Warning - bad CRC, using default environment

In:    serial@ff000000
Out:   serial@ff000000
Err:   serial@ff000000
Board: Xilinx ZynqMP
Bootmode: QSPI_MODE
Net:   ZYNQ GEM: ff0b0000, mdio bus ff0d0000, phyaddr 2, interface sgmii
Could not get PHY for eth0: addr 2
No ethernet found.
U-BOOT for petalinux

ZYNQ GEM: ff0b0000, mdio bus ff0d0000, phyaddr 2, interface sgmii
mdio_register: non unique device name 'eth0'
ZYNQ GEM: ff0b0000, mdio bus ff0d0000, phyaddr 2, interface sgmii
mdio_register: non unique device name 'eth0'
ZYNQ GEM: ff0b0000, mdio bus ff0d0000, phyaddr 2, interface sgmii
mdio_register: non unique device name 'eth0'
ZYNQ GEM: ff0b0000, mdio bus ff0d0000, phyaddr 2, interface sgmii
mdio_register: non unique device name 'eth0'
No ethernet found.
ZYNQ GEM: ff0b0000, mdio bus ff0d0000, phyaddr 2, interface sgmii
mdio_register: non unique device name 'eth0'
Hit any key to stop autoboot:  0
SF: Detected n25q1024a with page size 512 Bytes, erase size 128 KiB, total 256 MiB
device 0 offset 0x140000, size 0x1600000
SF: 23068672 bytes @ 0x140000 Read: OK
Wrong Image Format for bootm command
ERROR: can't get kernel image!
ZynqMP> gpio
gpio - query and control gpio pins

Usage:
gpio <input|set|clear|toggle> <pin>
    - input/set/clear/toggle the specified pin
gpio status [-a] [<bank> | <pin>]  - show [all/claimed] GPIOs
ZynqMP>
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