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krishn29
Newbie
Newbie
9,753 Views
Registered: ‎09-23-2013

Zynq(zedboard) Linux Software Resetting Programmable Logic alone

Hi Community,

 

I am working with the Digilent Zedboard .

I am trying to software reset the whole programmable logic(which uses FCLK_RESET0_N) from Linux.

I found that we can do it through the SLCR(System Level control Registers) and found slcr.c Platform driver(in linux-xlnx/arch/arm/mach-zynq) precompiled in the kernel which has xslcr_reset_periph() function to reset a peripheral.

I can see an entry  for the slcr in the device tree and also see it in

 

/sys/class/xslcr_reset/fpga0_out
 /sys/devices/amba.0/f8000000.ps7-slcr/xslcr_reset/fpga0_out/

 

I dont seem to have an entry in /dev  though

 

How do I use this driver to perform a reset?  Can I do it with a simple 'echo ' as shown for the power management driver in http://www.wiki.xilinx.com/Zynq+Power+Management ?

 

echo enabled > /sys/devices/amba.0/e0001000.serial/tty/ttyPS0/power
echo (rising|falling|both) > /sys/class/gpio/gpio<n>/edge

or Do I need to write a character device driver that communicates to the platform driver for this? ..Thanks in advance !

 

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10 Replies
sorenb
Xilinx Employee
Xilinx Employee
9,749 Views
Registered: ‎03-13-2012

Several things:

What do you mean with SW reset the whole PL? Asserting any of those FPGA reset lines does just toggle a signal which is routed to the PL. Depending on what you have connected to those signals something may be triggered, but they do not magically perform a reset of the PL.

 

IIRC, we removed the SLCR's sysfs interface because it never worked correctly and exposed some fucntionality, which should never have been exposed. AFAIK, there is no way to toggle the FPGA reset lines from Linux currently. The easiest work around would be to use a GPIO signal through EMIO as reset for you logic in the PL. GPIOs can be used as described e.g. on the wiki page you linked to.

krishn29
Newbie
Newbie
9,740 Views
Registered: ‎09-23-2013

Thank you so  much for the quick reply!

Let me clarify the ambiguities:

 

In XPS ,I have copnnections such that the whole of the Programmable Logic

is on  FCLK_CLK0 and the corresponding reset FCLK_RESET0_N.

So if I am able to toggle this signal from software,then I  should be able to reset the whole PL.

 

I have tried using a register which I write through AXI Lite to reset my accelerator  logic that

I wrote. However I am just worried that the AXI bus related logic is not getting reset

(I just want to reset the whole PL after one bus transaction to make sure that there

are no issues related to state  in any part of the PL including the AXI bus logic).

Hence I thought that if I could toggle FCLK_RESET0_N, I could reset the whole PL.

because it is connected to  everything in XPS

 

I cant ensure the  Logic handling the AXI bus protocol also gets reset by

using the EMIO ,right ? ( I think the bus arbitration etc logic is invisible to the  user as I have not seen it user_logic.v)

  or can I do this ?  Is there a solution to my problem?

 

Thanks again in advance!

 

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sorenb
Xilinx Employee
Xilinx Employee
9,737 Views
Registered: ‎03-13-2012

I'm not an expert in this area, but I think that the easiest work around would be to just replace all connections to FCLK_RESET0_N with some GPIO signal. You should be able to connect that GPIO signal to everything the other signal is currently connected to (at least I hope that is possible. Reset pins sometimes need some special reset signals, but usually this is possible somehow.)

The GPIO pins can be easily controlled from within Linux.

alazarut
Visitor
Visitor
9,644 Views
Registered: ‎10-29-2013

from linux the 4 reset lines are mapped into

/sys/class/xslcr_reset/fpga0_out/reset
/sys/class/xslcr_reset/fpga1_out/reset

/sys/class/xslcr_reset/fpga2_out/reset

/sys/class/xslcr_reset/fpga3_out/reset

 

to toggle them

 

echo 1 > /sys/class/xslcr_reset/fpga1_out/reset

 

or

 

echo 0 > /sys/class/xslcr_reset/fpga1_out/reset

 

 

Have fun,

Aurash

 

 

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sorenb
Xilinx Employee
Xilinx Employee
9,640 Views
Registered: ‎03-13-2012


@alazarut wrote:

from linux the 4 reset lines are mapped into

/sys/class/xslcr_reset/fpga0_out/reset
/sys/class/xslcr_reset/fpga1_out/reset

/sys/class/xslcr_reset/fpga2_out/reset

/sys/class/xslcr_reset/fpga3_out/reset


That interface is no longer existing on recent kernels. I highly recommend using GPIO.

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alazarut
Visitor
Visitor
9,628 Views
Registered: ‎10-29-2013

consider the following scenario

 

your GPIO used to reset things, is AXI_LITE slave device in PL, and you need to reset the AXI_slave bus, not a great idea.

another one

you reprogram the PL from linux, and you need to reset all busses, so you don't have a GPIO available yet (a typical chicken, egg problem)

 

I think the FCLK_RESETn lines are useful for reseting because are accessible from PS regardles of the state of PL, you can toggle them from fsbl, u-boot or linux. (the lineas are there you don't need to add an extra peripheral, nor consuming EMIOs)

 

 

Aurash

 

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sorenb
Xilinx Employee
Xilinx Employee
9,625 Views
Registered: ‎03-13-2012

I don't argue that they can be useful or anything. All I'm saying is:

1. Those signals are essentially nothing different than GPIOs with a fixed direction and no interrupt capability. So, everything you can implement with thse resets, should also be possible using GPIOs.

2. There is currently no interface to control these signals from Linux.

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kgregorian
Visitor
Visitor
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Registered: ‎11-14-2013

I agree with this completely.  The functionality is there, and it seems silly to burn a GPIO pin to recreate it.

 

The base address to the SLCRs (according to the slcr definition in my devicetree, check yours for 'ps7-slcr') is 0xf80000.  According to slcr.c, the offset for the FPGA reset lines 0x240.  This gives you some options. 

 

Here are 3 ways to do what you'd like:

 

1) /sbin/devmem 0xf8000240 32 0xF // resets ALL lines, 0x1 is RESET0, 0x2 RESET1 0x3 RESET0+RESET1

Be sure to write 0xf8000240 to 0x0 to bring it out of reset!

 

2) mmap /dev/mem and write it in C

3) (untested) change the devicetree "compatible" property to include "uio_pdrv_genirq" with a fake IRQ or modify uio_pdrv.c to read the compatible property.  In either case, this lets you use the UIO system to access these registers from userspace (see http://fpgacpu.wordpress.com/2013/05/28/how-to-design-and-access-a-memory-mapped-device-part-two/).

 

Keep in mind that, at least with 14.7 kernel, you DO NOT need to recompile your kernel unless you modify uio_pdrv.c  If you use the "fake" IRQ solution, it already comes in the stock kernel.

 

Hope this helps!  

 

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sschekall
Participant
Participant
9,420 Views
Registered: ‎10-27-2013

Are you saying that

 

SLCR..FPGA_RST_CTRL (@0xF8000240)   done not work?

 

I'm using the following function (Which does not seem to work). I would Like to know what is wrong with my code

 

 

//*****************************************************************************

// FPGA RST controller software reset from the slcr

//******************************************************************************

void XSlcr_FpgaReset(void) {

    u32 RegVal;  

   // Unlock the slcr register access lock

   Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);  

   // Assert the reset

   RegVal = Xil_In32(XSLCR_FPGA_RST_CTRL_ADDR);

   RegVal = RegVal | 0x0F; 

   Xil_Out32(XSLCR_FPGA_RST_CTRL_ADDR, RegVal);

   // delay  

   int i = 1024;  while (i-->0);

   //  Release the reset  

   RegVal = Xil_In32(XSLCR_FPGA_RST_CTRL_ADDR);

   RegVal = RegVal & ~0x0F;

   Xil_Out32(XSLCR_FPGA_RST_CTRL_ADDR,  RegVal);

   // Lock SLCR Block

    Xil_Out32(XSLCR_LOCK_ADDR, XSLCR_LOCK_CODE);  

   }

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s381168
Observer
Observer
2,108 Views
Registered: ‎02-09-2013

Did you ever get this function working?