Zynq7000, Xilinx DRM failed to request DMA

[jan_ch]

Hello,

I am working on Linux with GUI on the custom board with ADV7513. I have succesfully run the color bars with standalone application, and now on the same design i am trying to run gui but having problems with Xilinx DRM.

The design (brief) - AXI VDMA -> AXI4Stream subset converter -> rgb2ycbcr converter -> chroma resampler -> axi4stream to video out 

The video timing controller is also present. The rgb2ycbcr converter and chroma resampler have axi4lite configuration interface disabled. They are both configured in vivado. 

My devicetree looks like below:

                misc_clk_0: misc_clk_0 {
                        #clock-cells = <0>;
                        clock-frequency = <148500000>;
                        compatible = "fixed-clock";
                };

axi_iic_0: i2c@41600000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        clock-names = "s_axi_aclk";
                        clocks = <&clkc 15>;
                        compatible = "xlnx,axi-iic-2.0", "xlnx,xps-iic-2.00.a";
                        interrupt-names = "iic2intc_irpt";
                        interrupt-parent = <&intc>;
                        interrupts = <0 30 4>;
                        reg = <0x41600000 0x10000>;
                        adv7513: adv7513@39 {
                                compatible = "adi,adv7513";
                                reg = <0x39>;
                                adi,input-depth = <8>;
                                adi,input-colorspace = "yuv422";
                                adi,input-clock = "1x";
                                adi,input-style = <1>;
                                adi,input-justification = "evenly";
                                adi,input-id = <0x01>;
                                adi,input-color-depth = <0x3>;
                                adi,sync-pulse = <0x03>;
                                adi,up-conversion = <0x00>;
                                adi,timing-generation-sequence = <0x00>;
                                adi,vsync-polarity = <0x02>;
                                adi,hsync-polarity = <0x02>;
                                adi,tdms-clock-inversion;
                                adi,clock-delay = <0x03>;

                        };
                };
                dma: dma@43000000 {
                        #dma-cells = <1>;
                        clocks = <&clkc 15>, <&clkc 16>, <&clkc 16>;
                        clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axis_mm2s_aclk";
                        compatible = "xlnx,axi-vdma-6.3", "xlnx,axi-vdma-1.00.a";
                        interrupt-names = "mm2s_introut";
                        interrupt-parent = <&intc>;
                        interrupts = <0 29 4>;
                        reg = <0x43000000 0x10000>;
                        xlnx,addrwidth = <0x20>;
                        xlnx,flush-fsync = <0x1>;
                        xlnx,num-fstores = <0x1>;
                        dma-channel@43000000 {
                                compatible = "xlnx,axi-vdma-mm2s-channel";
                                interrupts = <0 29 4>;
                                xlnx,datawidth = <0x20>;
                                xlnx,device-id = <0x0>;
                                xlnx,include-dre ;
                        };
                };
                v_tc_0: v_tc@43c00000 {
                        clock-names = "clk", "s_axi_aclk";
                        clocks = <&misc_clk_0>, <&clkc 15>;
                        compatible = "xlnx,v-tc-6.1", "xlnx,v-tc-6.1";
                        reg = <0x43c00000 0x10000>;
                        xlnx,generator ;
                };

                xilinx_drm: xilinx_drm {
                    compatible = "xlnx,drm";
                    xlnx,vtc = <&v_tc_0>;
                    xlnx,encoder-slave = <&adv7513>;
                    xlnx,connector-type = "HDMIA";
                    clocks = <&misc_clk_0>;

                    planes {
                        xlnx,pixel-format = "yuv422";
                        plane0 {
                            dma = <&dma 0>;
                            dma-names = "dma";
                        };
                    };
                };

My first problem is with DRM:

xilinx-vdma 43000000.dma: Xilinx AXI VDMA Engine Driver Probed!!
[drm:xilinx_drm_plane_create] *ERROR* failed to request dma channel "dma" for plane /amba_pl/xilinx_drm/planes/plane0 (err:-19)
[drm:xilinx_drm_plane_create_primary] *ERROR* failed to allocate a primary plane
[drm:xilinx_drm_crtc_create] *ERROR* failed to create a primary plane for crtc

Second is with ADV7513 (My question is about the first problem but maybe the second will give more light to the problem)

adv7511 1-0039: 1-0039 supply avdd not found, using dummy regulator
adv7511 1-0039: 1-0039 supply dvdd not found, using dummy regulator
adv7511 1-0039: 1-0039 supply pvdd not found, using dummy regulator
adv7511 1-0039: 1-0039 supply bgvdd not found, using dummy regulator
adv7511 1-0039: 1-0039 supply dvdd-3v not found, using dummy regulator
i2c i2c-1: Failed to register i2c client dummy at 0x3b (-16)
adv7511: probe of 1-0039 failed with error -12
Error: Driver 'adv7511' is already registered, aborting...

Please help me to resolve this issue

Regards,

JCH

[florentw]

HI @jan_ch 

I do not think you will be able to connect the DMA directly to the ADV7511. You might need to use the Video Mixer IP in between.

Refer to this wiki page

[jan_ch]

The VDMA is not directly connected to ADV7511:

As I wrote the is in a chain : AXI VDMA -> AXI4Stream subset converter -> rgb2ycbcr converter -> chroma resampler -> axi4stream to video out

Regards

[florentw · Accepted solution]

Hi @jan_ch 

Yes but none of the IP connected has a DRM driver.

I think you need at least one in the pipe, this is why I am suggesting the video mixer. Please have a look to the mentioned wiki page