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Prasanna_K
Explorer
Explorer
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Registered: ‎07-24-2020

ZynqMP: petalinux hangs when starting u-boot

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Hello Everyone,

I am trying to boot petalinux on ZynqMP using SD boot mode, however it fails at u-boot. I have enabled FSBL debug to see more option but still not sure why it is failing.

Xilinx Zynq MP First Stage Boot Loader
Release 2019.2   Nov 27 2020  -  09:02:22
Reset Mode      :       System Reset
Platform: Silicon (4.0), Cluster ID 0x80000000
Running on A53-0 (64-bit) Processor, Device Name: XCZU19EG
Processor Initialization Done
================= In Stage 2 ============
SD1 Boot Mode
SD: rc= 0
File name is BOOT.BIN
Multiboot Reg : 0x0
Image Header Table Offset 0x8C0
*****Image Header Table Details********
Boot Gen Ver: 0x1020000
No of Partitions: 0x4
Partition Header Address: 0x440
Partition Present Device: 0x0
Initialization Success
======= In Stage 3, Partition No:1 =======
UnEncrypted data Length: 0x8AA352
Data word offset: 0x8AA352
Total Data word length: 0x8AA352
Destination Load Address: 0xFFFFFFFF
Execution Address: 0x0
Data word offset: 0xE9A0
Partition Attributes: 0x26
Destination Device is PL, changing LoadAddress
Non authenticated Bitstream download to start now
DMA transfer done
PL Configuration done successfully
Partition 1 Load Success
======= In Stage 3, Partition No:2 =======
UnEncrypted data Length: 0x31DE
Data word offset: 0x31DE
Total Data word length: 0x31DE
Destination Load Address: 0xFFFEA000
Execution Address: 0xFFFEA000
Data word offset: 0x8B8D00
Partition Attributes: 0x117
Partition 2 Load Success
======= In Stage 3, Partition No:3 =======
UnEncrypted data Length: 0x2D964
Data word offset: 0x2D964
Total Data word length: 0x2D964
Destination Load Address: 0x8000000
Execution Address: 0x8000000
Data word offset: 0x8BBEE0
Partition Attributes: 0x114
Partition 3 Load Success
All Partitions Loaded
================= In Stage 4 ============
PM Init Success
Protection configuration applied
Running ▒ꊕ5▒J
iU▒▒*▒ͥ▒▒▒▒▒▒▒ѽ▒Q1չ▒▒▒▒▒▒▒▒a
                   с▒�▒▒▒▒▒▒jR▒▒5▒J1▒▒▒▒▒▒▒ɕ▒▒▒▒▒▒▒с▒▒▒5Rr▒E▒5▒J1▒▒▒r▒▒▒͕▒▒ɕ▒▒▒▒▒▒▒с▒▒▒▒▒▒▒▒jR▒NOTICE:  BL31: v2.0(release):xilinx-v2019.1-12-g713dace9
NOTICE:  BL31: Built : 08:59:45, Nov 27 2020
PMUFW:  v1.1


U-Boot 2019.01 (Nov 27 2020 - 08:59:42 +0000) Xilinx ZynqMP IWG35M

Board: iW-RainboW-G35M based on Zynq Ultrascale+ MPSoC

Updated dr_mode property to host
DRAM:  4 GiB
EL Level:       EL2
Chip ID:        zu19eg

 

Regards,

Prasanna

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Prasanna_K
Explorer
Explorer
766 Views
Registered: ‎07-24-2020

Hi @watari @patocarr ,

Thank you for your input!! 

I was able to resolve the issue by importing my vendors settings in vivado. Not sure though for what exact reason it was failing  but after importing all the setting from vendor's design(ZynqMP IP) in vivado, OS booted successfully. 

Regards,

Prasanna

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7 Replies
watari
Teacher
Teacher
927 Views
Registered: ‎06-16-2013

Hi @Prasanna_K 

 

What kid of board are you using ? Xilinx evaluation board ? Your own designed board ?

 

It seems power issue or dram issue...

But it's difficult to find the route cause without details...

 

Best regards,

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Prasanna_K
Explorer
Explorer
875 Views
Registered: ‎07-24-2020

Hi @watari ,

Thanks for your reply,

It's an evaluation board from Xilinx partner company(Part number: XCZU19EG).

I was able to boot the OS using the XSA provided by the partner company. However, when I tried to boot using my design, it hangs at this point. The steps followed to compile the boot images are the same but the only difference is that the XSA is different.

So do I need to make some configuration changes to Zynq IP block in the vivado??  Or is there a way to enable debug prints for u-boot? I have enabled debug prints for FSBL but not sure how to enable the same for u-boot, if it is documented somewhere, please let me know.

Regards,

Prasanna

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patocarr
Teacher
Teacher
826 Views
Registered: ‎01-28-2008

Hi @Prasanna_K 

  You should have better luck starting your design using the vendor's board flow for that eval board, or lacking that, using the firmware/Zynq IP configuration from the vendor's design and copied into yours. It's possible some memory or clock configuration is not properly set if you haven't modified the PS configuration to match the hardware.

Thanks,

-Pat

 

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

watari
Teacher
Teacher
811 Views
Registered: ‎06-16-2013

Hi @Prasanna_K 

 

OK.

According to your log file and your explanation, it seems DRAM parameter issue or pll issue or power lane issue.

Would you make sure difference of DRAM parameter and pll setting between vendor's design and yours by Vivado, first ?

 

Best regards,

Prasanna_K
Explorer
Explorer
767 Views
Registered: ‎07-24-2020

Hi @watari @patocarr ,

Thank you for your input!! 

I was able to resolve the issue by importing my vendors settings in vivado. Not sure though for what exact reason it was failing  but after importing all the setting from vendor's design(ZynqMP IP) in vivado, OS booted successfully. 

Regards,

Prasanna

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dreaguns
Participant
Participant
268 Views
Registered: ‎05-30-2019

I'm trying to bootup a zynqMP eval board with Petalinux from SD card as well.

Do you have a reference to the process flow? 

I'm on a windows machine..., did you use the PetaLinux SDK?

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Prasanna_K
Explorer
Explorer
221 Views
Registered: ‎07-24-2020

Hi @dreaguns ,

Yes, I have used Petalinux SDK wherein I have created project using a template instead of BSP as shown below

petalinux-create --type project --template zynqMP --name <Name of project>

Then you can follow the petalinux flow to complete the image process. 

Regards,

Prasanna

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