07-16-2020 05:57 PM - edited 07-16-2020 07:13 PM
I am dynamically changing an fclk (on a Zynq UltraScale+ MPSoC) from petalinux 2019.2 and I've noticed that sometimes I get different values. The command I use is like the following:
echo 15000000 > /sys/devices/platform/fclk1/set_rate && cat /sys/devices/platform/fclk1/set_rate 15625000
This is fine, I know I won't get exact clocks all the time; however, after switching to a few other frequencies, then switching back, I get:
echo 15000000 > /sys/devices/platform/fclk1/set_rate && cat /sys/devices/platform/fclk1/set_rate 15000000
Which is great, yay! But then more switching speeds and back to this:
echo 15000000 > /sys/devices/platform/fclk1/set_rate && cat /sys/devices/platform/fclk1/set_rate 15306123
What is going on?
So I expect more repeatability than I'm seeing here. Is this some weirdness with the PLL dividers or a bad kernel round_rate? How can I fix this?
07-28-2020 03:32 PM
I don't know if it helps, but I know there is a problem with drivers/clk/zynqmp/divider.c before 2019.2.
This issue has been fixed in 2020.1.
Perhaps this is the fix for this issue.
It has already been fixed in the Linux Kernel mainline.
If it is good in Japanese language, the explanation of the problem is explained in the next article. Please translate and refer.
08-17-2020 12:44 PM
We attempted to apply that kernel patch but all the source changes are already found in the `xilinx-v2019.2.01` kernel tag and the fclk set_rate method still can return various frequencies.
Additionally we built petalinux 2020.1 to see if it indeed fixed the problem and found that the fclk module doesn't even work - using the sysfs fclk set_rate method mentioned above fails to change the fclk to anything and it is always the default as enabled in the MPSoC block in Vivado.
I'm not sure what to try next.
08-17-2020 06:34 PM - edited 08-17-2020 06:36 PM
Sorry. The linux-xlnx commit didn't solve this problem yet.
Apply the following patch to xilinx-v2019.2.01,
or use xilinx-v2020.2.
Addendum: I'm not sure that the fclk driver is not working on xilinx-v2020.1. I am not using the fclk provided by xilinx due to the inability to safely change the frequency.