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buckd
Contributor
Contributor
1,278 Views
Registered: ‎08-13-2016

fclk kernel module and rounding or PLL division errors

Hi,

I am dynamically changing an fclk (on a Zynq UltraScale+ MPSoC) from petalinux 2019.2 and I've noticed that sometimes I get different values. The command I use is like the following:

echo 15000000 > /sys/devices/platform/fclk1/set_rate && cat /sys/devices/platform/fclk1/set_rate
15625000

This is fine, I know I won't get exact clocks all the time; however, after switching to a few other frequencies, then switching back, I get:

echo 15000000 > /sys/devices/platform/fclk1/set_rate && cat /sys/devices/platform/fclk1/set_rate
15000000

Which is great, yay! But then more switching speeds and back to this:

echo 15000000 > /sys/devices/platform/fclk1/set_rate && cat /sys/devices/platform/fclk1/set_rate
15306123

Rats!

What is going on?

So I expect more repeatability than I'm seeing here. Is this some weirdness with the PLL dividers or a bad kernel round_rate? How can I fix this?

Thanks!

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9 Replies
watari
Professor
Professor
1,256 Views
Registered: ‎06-16-2013

Hi @buckd 

 

What petalinux version are you using ?

I'm not sure, but, perhaps I may know it...

 

Best regards,

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buckd
Contributor
Contributor
1,250 Views
Registered: ‎08-13-2016

Xilinx tools 2019.2. Post above updated.

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buckd
Contributor
Contributor
1,121 Views
Registered: ‎08-13-2016

Hi again,

I have still not found information on how to predict the PLL dividers for the fclks.

Does anyone have more information?

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kawazome
Adventurer
Adventurer
1,103 Views
Registered: ‎04-02-2014

 

I don't know if it helps, but I know there is a problem with drivers/clk/zynqmp/divider.c before 2019.2.

This issue has been fixed in 2020.1.
Perhaps this is the fix for this issue.

https://github.com/Xilinx/linux-xlnx/commit/3da97fb5ebf6e0568a325b37d4bbe5dad898cef4

 

It has already been fixed in the Linux Kernel mainline.

https://lkml.org/lkml/2019/11/7/173

 

If it is good in Japanese language, the explanation of the problem is explained in the next article. Please translate and refer.

https://qiita.com/ikwzm/items/f19669462ece632db040

 

 

buckd
Contributor
Contributor
1,049 Views
Registered: ‎08-13-2016

This looks like exactly the issue. I'll try it and see if it fixes things. Thanks!

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buckd
Contributor
Contributor
961 Views
Registered: ‎08-13-2016

Hi again,

We attempted to apply that kernel patch but all the source changes are already found in the `xilinx-v2019.2.01` kernel tag and the fclk set_rate method still can return various frequencies.

Additionally we built petalinux 2020.1 to see if it indeed fixed the problem and found that the fclk module doesn't even work - using the sysfs fclk set_rate method mentioned above fails to change the fclk to anything and it is always the default as enabled in the MPSoC block in Vivado.

I'm not sure what to try next.

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kawazome
Adventurer
Adventurer
876 Views
Registered: ‎04-02-2014

Sorry. The linux-xlnx commit didn't solve this problem yet.

Apply the following patch to xilinx-v2019.2.01,

https://github.com/ikwzm/ZynqMP-FPGA-Linux/blob/v2019.2.1/files/linux-xlnx-v2019.2-zynqmp-fpga-clk-divider.diff

or use xilinx-v2020.2.


Addendum: I'm not sure that the fclk driver is not working on xilinx-v2020.1. I am not using the fclk provided by xilinx due to the inability to safely change the frequency.

MichaelK
Contributor
Contributor
450 Views
Registered: ‎06-25-2020

Hey @buckd 
Is there any info on why the fclk is not working for you in 2020.1? I'm facing the same issue.

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buckd
Contributor
Contributor
414 Views
Registered: ‎08-13-2016

No, I only know that the error persists in 2020.1. The patch from kawazome above did fix it for 2019.2.1.

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