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Contributor
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Registered: ‎04-18-2016

fpga manager : bitstream loading not working 2018.2

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Trying to load bitstream using the FPGA manager in petalinux 2018.2 hangs the whole

system. I followed the instructions at http://www.wiki.xilinx.com/Solution+ZynqMP+PL+Programming

I have a ZCU102 , with an ES2 part.  If I load the same bitstream using JTAG is works fine.

 

Also if I use petalinux 2017.4 I can use the FPGA manager and follow the same instructions and it works.

 

Any ideas  ??

 

Sandeep

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-22-2018

This issue seems to be with bitstream image format.

The Bootgen Command for generating the bin file from bit got changed from 2018.1 release onwards.

bootgen -image Bitstream.bif -arch zynqmp -o ./Bitstream.bin -w

This info was Documented in the below link (Refer this section: Generating .bin from .bit file using Bootgen)
http://www.wiki.xilinx.com/Solution+ZynqMP+PL+Programming.

 

Please try with the about  command and let me know your observations.

 

 

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Moderator
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Registered: ‎09-12-2007
Can yhiu show the boot log up to the crash,
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Contributor
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Registered: ‎04-18-2016

The system boots normally. I am trying to load the bitstream from the command line. 

Here is what I see

root@xilinx-zcu102-zu9-es2-rev1_0-2018_2:~/bits# echo vsi_system_zynqMP_pl_hier_0.bit.bin > /sys/class/fpga_manager/fpga0/firmware
[ 49.981122] fpga_manager fpga0: writing vsi_system_zynqMP_pl_hier_0.bit.bin to Xilinx ZynqMP FPGA Manager 

 

The system freezes at this point. I notice that the "INIT" Led is green , the "Done"  LED remains low. The same command with the same bitstream works fine if I use 2017.4.

 

Best

Sandeep

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Registered: ‎04-18-2016

Attached boot log for boot 2017.4 (working) & 2018.1 (not working) with the same bitstream.

 

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Contributor
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Registered: ‎04-18-2016

I tried with the Ultra96 (2018.2) same problem, any solution for this would be appreciated.

 

 

sandeep

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Voyager
Voyager
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Registered: ‎09-14-2016

Hi @sandeepdutta,

 

 

# echo vsi_system_zynqMP_pl_hier_0.bit.bin > /sys/class/fpga_manager/fpga0/firmware 

Try with cat command :

 

# cat vsi_system_zynqMP_pl_hier_0.bit.bin > /dev/xdevcfg

Not sure because i'm on Zynq and not ZynMP :S

 

 

[EDIT]: After some tests on a custom board base on Zynq7000 echo commande doesn't work ...

 

[ 5594.037260] Did not transfer last 3 bytes

Maybe you should also take a look to bit/bin format ... Maybe ... Maybe not :S

 

Cheers,

Trigger

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Contributor
Contributor
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Registered: ‎04-18-2016
Thank you Trigger, unfortunately /dev/xdevcfg has been deprecated
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Xilinx Employee
Xilinx Employee
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Registered: ‎02-18-2014

Could you please share the bit file and top level vivado block diagram if possible?? 

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Xilinx Employee
Xilinx Employee
4,332 Views
Registered: ‎09-22-2018

This issue seems to be with bitstream image format.

The Bootgen Command for generating the bin file from bit got changed from 2018.1 release onwards.

bootgen -image Bitstream.bif -arch zynqmp -o ./Bitstream.bin -w

This info was Documented in the below link (Refer this section: Generating .bin from .bit file using Bootgen)
http://www.wiki.xilinx.com/Solution+ZynqMP+PL+Programming.

 

Please try with the about  command and let me know your observations.

 

 

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Contributor
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Registered: ‎04-18-2016

Thank you Navam,

 

That was the problem...

Best Regards

Sandeep

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Contributor
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Registered: ‎06-30-2014

I realize this was nearly a year ago, but today the command shown on that wiki is: bootgen -image file.bif -arch zynqmp -process_bitstream bin.  And it doesn't work for me.  Several seconds after attempting to write the resulting image to the manager, the kernel panics.  If I use the command provided above in this forum, the resulting image writes immediately to the FPGA without issues.  (Vivado 2018.3)

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Observer
Observer
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Registered: ‎05-29-2018

I have the same question ,but this method did not work.

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