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linux SPI for zynq

Observer
Posts: 27
Registered: ‎02-19-2014

linux SPI for zynq

Hi,

 

I’ would like to use Peripheral  spi:0 of Zynq Xilinx with Linux OS on the ZC706 . And I selec /device driver/SPI support/Xilinx SPI controller common module in the menu, so SPIDEV is built in the uImage. And zynq-zc706.dts is added the following sentence for SPI.

        spi_0: spi@e0006000 {
            compatible = "xlnx,ps7-spi-1.00.a";
            reg = <0xE0006000 0x1000>;
            interrupts = <0 26 4>;
            interrupt-parent = <&ps7_scugic_0>;
            speed-hz = <166666672>;
            bus-num = <0>;
            num-chip-select = <3>;
            #address-cells = <1>;
            #size-cells = <0>;
                  spidev@0 {
                      compatible = "spidev";
                      reg = <0>;  /* CS */
                      spi-max-frequency = <25000000>;
                      /*spi-cpha; Possible property */
                      /*spi-cpol; Possible property */
                      /*spi-cs-high; Possible property */
                      /*spi-3wire; Possible property */
                      /*no interrupts */
            };
        }

 

unfortunately, SPI driver can not loaded correctly, I do not find spi device in the /dev folder and the log is as following:

xspips e0006000.spi: aper_clk clock not found.
xspips: probe of e0006000.spi failed with error -2


I got linux and uboot from

https://github.com/Xilinx/linux-xlnx/releases/tag/xilinx-v2013.4

 

I used the following version

linux kernel version: v2013.4

uboot version: v2013.4

 

Xilinx Employee
Posts: 444
Registered: ‎03-13-2012

Re: linux SPI for zynq

You're missing 'clocks' and 'clock-names' properties in your DT (cmp: https://github.com/Xilinx/linux-xlnx/blob/master-next/arch/arm/boot/dts/zynq-zc770-xm010.dts#L316 ).

Visitor
Posts: 24
Registered: ‎10-02-2013

Re: linux SPI for zynq

I'm having similar trouble.  I can successfully control SPI with bare metal code.  I'm trying to transition to Linux and really struggling with the SPI.  Does anyone actually have it working in Linux with a ZC706?  I have SP0 enabled as EMIO.  I have the latest kernel compiled with SPIDEV.  My devicetree has the clocks as mentioned by sorenb.  It is:

		ps7_spi_0: ps7-spi@e0006000 {
			clock-names = "ref_clk", "aper_clk";
			clocks = <&clkc 25>, <&clkc 34>;
			compatible = "xlnx,ps7-spi-1.00.a";
			interrupt-parent = <&ps7_scugic_0>;
			interrupts = <0 26 4>;
			num-chip-select = <4>;
			reg = <0xe0006000 0x1000>;
			#address-cells=<1>;
			#size-cells=<0>;
			spidev@0{
				compatible="spidev";
				reg =<0>; //chipselect 0
				spi-max-frequency= <50000000>;
			};
			spidev@1{
				compatible="spidev";
				reg =<1>; //chipselect 1
				spi-max-frequency= <50000000>;
			};
			spidev@2{
				compatible="spidev";
				reg =<2>; //chipselect 2
				spi-max-frequency= <50000000>;
			};
		} ;

 My tree was generated by the device tree generator tool, and I added everything from #address-cells=<1> down.

 

I have my SS1 and SS2 wired to the FMC connector going to a SPI controled ADC card.  Again, I can control the ADC over SPI perfectly with the bare_metal BSP code.

 

In Linux I get /dev/spidev1.0, /dev/spidev1.1, and /dev/spidev1.2.  When I run spidev_test on either spidev1.1 or spidev 1.2, I can see the correct chip select getting set on a scope.  However, Linux completely locks up on the transmit attempt and the scope shows a SCLK (clock) that both doesn't look correct and never stops.

 

I've run out of ideas on how to further debug this so any comments/suggestions would be welcomed!

Xilinx Employee
Posts: 444
Registered: ‎03-13-2012

Re: linux SPI for zynq

I'm certainly not a SPI expert, so just some generic advice:

It sounds like you may run in some deadlock. Do you have deadlock debugging/detection enabled (cmp: https://github.com/Xilinx/linux-xlnx/commit/e8a0f03e48a0b28fb2d8137745bc7dd9da61d724 ). That might give some additional hints where a deadlock may be originating from.

Visitor
Posts: 24
Registered: ‎10-02-2013

Re: linux SPI for zynq

Ok.  That's digging in to the kernel a bit more than I'm ready for at the moment.  My SPI needs are limited (simple polled writing).  So for now, I wrote a simple HLS block to do my SPI and that works so I'm moving on.  I'd rather use the built-in SPI, but I'll have to try your debug suggestions later.  Thanks.

Observer
Posts: 27
Registered: ‎02-19-2014

Re: linux SPI for zynq

I did not verify whether SPI be controlled with bare metal code based on standalone.I changed dts that is same to your dts. and i investigate this issue that seems halted in the wait_for_completion from xspips_start_transfer. I am not sure FPGA bitstream has been loaded successfully, which is provided by xilinx FAE engineer, and just SPI control MSIO pin is connected to the FPGA pin. any suggestion is welcome.thanks.

 

ps, register value from SPI controller register is shown as the following.
0xf0068000 0000fc21 00000004 00000000 00000000
0xf0068010 00000000 00000001 00000000 00000000
0xf0068020 00000000 000000ff 00000001 00000001
reg:0xf00680fc 00090106

Observer
Posts: 27
Registered: ‎02-19-2014

Re: linux SPI for zynq

I found FPGA done led is light.but still wait_for_completion not be finished.

Observer
Posts: 27
Registered: ‎02-19-2014

Re: linux SPI for zynq

to investigate this issue, MOSI is connected to MISO in FPGA. But this issue is the same as before. any suggestion? thanks.

spi_lp.PNG
Scholar
Posts: 416
Registered: ‎05-28-2013

Re: linux SPI for zynq

A patch to prevent getting stuck in wait_for_completion is here https://github.com/Xilinx/linux-xlnx/commit/07e258388ac3433afdfa27460c340f3e737cb3d4

However that will not make the actual transfer work... I suggest checking that you have clocks correctly configured and enabled... if the SPI controller doesn't receive a clock, it will most certainly not work!


Also I noticed a potential bug in the SPI driver, relating to setting the final clock divider:

while ((baud_rate_val < 8) && (frequency /(2 << baud_rate_val)) > req_hz)
baud_rate_val++;

Upon exit from the loop, baud_rate_val could be 8. However the max value permitted is 7 according to the Zynq TRM. When written to the control register at E000600, the baud_rate_val=8 actually spills over into an adjacent field that is reserved ("write 00").
Scholar
Posts: 416
Registered: ‎05-28-2013

Re: linux SPI for zynq

Update: if you are using SS0 for your chip select, then check this known issue: http://www.xilinx.com/support/answers/47511.htm

After fixing that in our PL, using a scope we are seeing the correct signals on EMIO for SPI device.