working on zynq ultrascale+ - bare metal on R5 and Linux on A53
I send data from R5 to A53 via OCM or DDR RAM okay but not the other direction.
On the original zynq I got bi-directional communications between the two cores via OCM with on core running bare metal and other Linux.
Any ideas what I'm doing wrong?
did some more tests and this may be a problem with my own code and not the hardware