UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor mugilvanan
Visitor
477 Views
Registered: ‎10-12-2017

system-top.dts

Hi,

      I created a petalinux project using the details provided in the link - https://www.google.co.in/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwi4gcuh_urWAhUHPI8KHUWXDxcQFggnMAA&url=http%3A%2F%2Fwww.wiki.xilinx.com%2FZynq%2BPL%2BEthernet&usg=AOvVaw08cET19uLgJCsaI5g0vgkF . It worked as expected. Now, I added my own logic to the hardware design. For instance, an extra AXI-DMA which will pass streaming data to FIFO and has nothing to do with AXI-DMA(the other one) and AXI-ETHERNET part. So, this has nothing to affect the ethernet working. The problem is, I have to modify system-top.dts in device tree. Is there any documentation that tells about how to create and edit system-top.dts?

 

If yes, please send the link. 

 

Thank you 

 

0 Kudos