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Observer matzik
Observer
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Registered: ‎10-18-2017

u-boot: reset phy through PL

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I have a couple of boards and for some of them I reach phy through PL.

I have to let fsbl load the PL before u-boot starts.

 

I also need to release the phy reset by writing to PL memory address.

In order to fix that, I add change zynq_phy_init early on to contain a write to a specific address in FPGA memory space.

 

I would rather solve it without changing zynq_gem:

By using mw and/or writing to the phy registers from the u-boot shell.

Or by writing something in the dts file that solved the problem.

 

Something like "phy-reset-gpios = <&gpioctlr 43 GPIO_ACTIVE_LOW>;", but writing to a memory address.

 

Is there such a solution?

 

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Voyager
Voyager
1,180 Views
Registered: ‎06-24-2013

Re: u-boot: reset phy through PL

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Hey @matzik,

 

From the fact that you use u-boot and talk of FSBL loading the PL I conclude that you are using a ZYNQ device, in which case the 'FPGA memory space' you are referring to is just memory mapped register space (most likely one of the AXI GP Ports). This means that you can use mw to write to those addresses in u-boot.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
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Voyager
Voyager
1,181 Views
Registered: ‎06-24-2013

Re: u-boot: reset phy through PL

Jump to solution

Hey @matzik,

 

From the fact that you use u-boot and talk of FSBL loading the PL I conclude that you are using a ZYNQ device, in which case the 'FPGA memory space' you are referring to is just memory mapped register space (most likely one of the AXI GP Ports). This means that you can use mw to write to those addresses in u-boot.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
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