cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
lrocher
Observer
Observer
3,560 Views
Registered: ‎09-28-2017

vcu problem

Jump to solution

I create a design like pg252-vcu.pdf  in vivado.

but when i start linux with petalinux. i have this message :


[   15.129865] udevd[1655]: starting version 3.2.2
[   15.250688] udevd[1656]: starting eudev-3.2.2
[   15.328177] mali: loading out-of-tree module taints kernel.

 

and the boot processing stop.

 

do you have an idea ?

0 Kudos
1 Solution

Accepted Solutions
lrocher
Observer
Observer
3,496 Views
Registered: ‎09-28-2017

hi,

i find one problem the DTG don't write the correct address

 

               vcu_0: vcu@80000000 {
                        #address-cells = <2>;
                        #size-cells = <2>;
                        clock-names = "pll_ref", "aclk";
                        clocks = <&misc_clk_0>, <&clk 71>;
                        compatible = "xlnx,vcu-1.1", "xlnx,vcu";
                        interrupt-names = "vcu_host_interrupt";
                        interrupt-parent = <&gic>;
                        interrupts = <0 89 4>;
                        ranges ;
                        reg = <0x0 0xa0040000 0x0 0x1000>,
                                <0x0 0xa0041000 0x0 0x1000>;
                        reg-names = "vcu_slcr", "logicore";
                        encoder: al5e@a0000000 {
                                compatible = "al,al5e-1.1", "al,al5e";
                                interrupt-parent = <&gic>;
                                interrupts = <0 89 4>;
                                reg = <0x0 0xa0000000 0x0 0x10000>;
                        };
                        decoder: al5d@a0020000 {
                                compatible = "al,al5d-1.1", "al,al5d";
                                interrupt-parent = <&gic>;
                                interrupts = <0 89 4>;
                                reg = <0x0 0xa0020000 0x0 0x10000>;
                        };
                };
                misc_clk_0: misc_clk_0 {
                        #clock-cells = <0>;
                        clock-frequency = <33000920>;
                        compatible = "fixed-clock";
                };

 

but i always a problem because no i stop with the message :

 

[ 4.742160] udevd[1677]: starting version 3.2.2
[ 4.858183] udevd[1678]: starting eudev-3.2.2
[ 4.947380] mali: loading out-of-tree module taints kernel.
[ 4.983992] xilinx-vcu 80040000.vcu: failed to set logicoreIP refclk rate
[ 4.991721] xilinx-vcu 80040000.vcu: xvcu_probe: Probed successfully

 

i think there are another problem but i don't know where if you are an idea

 

thanks

 

View solution in original post

0 Kudos
11 Replies
sandeepg
Moderator
Moderator
3,529 Views
Registered: ‎04-24-2017

Looks like something messed up in VCU IP drivers/device-tree/bitstream/clks.

 

Why don't you start with VCU TRD design https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841952/Technical+Articles#TRD 

 

In 2018.1/2 DTG does't generated right nodes for VCU IP for single and multi pipeline.

Thanks,
Sandeep
PetaLinux Yocto | Embedded SW Support

---------------------------------------------------------------------------
Don’t forget to Reply, Kudo, and Accept as Solution.
---------------------------------------------------------------------------
lrocher
Observer
Observer
3,514 Views
Registered: ‎09-28-2017

I am not start with the vcu trd, because I don't have the same board and the same components (xczu4ev-sfvc784-1-e).

I don't understand the problem with the DTG with 2018.1/2.

can i have more explaination?

 

and i make a very sample design in vivado

 

 

Capture.PNGthanks

 

0 Kudos
lrocher
Observer
Observer
3,497 Views
Registered: ‎09-28-2017

hi,

i find one problem the DTG don't write the correct address

 

               vcu_0: vcu@80000000 {
                        #address-cells = <2>;
                        #size-cells = <2>;
                        clock-names = "pll_ref", "aclk";
                        clocks = <&misc_clk_0>, <&clk 71>;
                        compatible = "xlnx,vcu-1.1", "xlnx,vcu";
                        interrupt-names = "vcu_host_interrupt";
                        interrupt-parent = <&gic>;
                        interrupts = <0 89 4>;
                        ranges ;
                        reg = <0x0 0xa0040000 0x0 0x1000>,
                                <0x0 0xa0041000 0x0 0x1000>;
                        reg-names = "vcu_slcr", "logicore";
                        encoder: al5e@a0000000 {
                                compatible = "al,al5e-1.1", "al,al5e";
                                interrupt-parent = <&gic>;
                                interrupts = <0 89 4>;
                                reg = <0x0 0xa0000000 0x0 0x10000>;
                        };
                        decoder: al5d@a0020000 {
                                compatible = "al,al5d-1.1", "al,al5d";
                                interrupt-parent = <&gic>;
                                interrupts = <0 89 4>;
                                reg = <0x0 0xa0020000 0x0 0x10000>;
                        };
                };
                misc_clk_0: misc_clk_0 {
                        #clock-cells = <0>;
                        clock-frequency = <33000920>;
                        compatible = "fixed-clock";
                };

 

but i always a problem because no i stop with the message :

 

[ 4.742160] udevd[1677]: starting version 3.2.2
[ 4.858183] udevd[1678]: starting eudev-3.2.2
[ 4.947380] mali: loading out-of-tree module taints kernel.
[ 4.983992] xilinx-vcu 80040000.vcu: failed to set logicoreIP refclk rate
[ 4.991721] xilinx-vcu 80040000.vcu: xvcu_probe: Probed successfully

 

i think there are another problem but i don't know where if you are an idea

 

thanks

 

View solution in original post

0 Kudos
radimsosty
Visitor
Visitor
3,421 Views
Registered: ‎01-19-2015

Hello @lrocher,

 

Try to use M_AXI_HPM0_FPD instead of M_AXI_HPM0_LPD. I had the same problem and this solved it.

 

However, this only helped me to boot petalinux, I'm still unable to use VCU and I don't know why ...

0 Kudos
lrocher
Observer
Observer
3,419 Views
Registered: ‎09-28-2017

hi,

 

you must have encoder and decoder in your fpga. because the device tree generator load the encoder en decoder.

you can check in your pl.dtsi file

lrocher
Observer
Observer
3,418 Views
Registered: ‎09-28-2017

to test the vcu, i copy a yuv file on my file system and i execute this command :

 

gst-launch-1.0 filesrc location="test.yuv" ! videoparse format=nv12 width=1920 height=1080 framerate=25/1 ! omxh264enc ! filesink location="out.h264"

 

0 Kudos
sandeepg
Moderator
Moderator
3,402 Views
Registered: ‎04-24-2017

Hi @lrocher,

 

If you have enabled DP in your VCU design then I would suggest to run simple pipeline.

 

Before you run the pipeline just run the QoS settings https://github.com/Xilinx/meta-petalinux/blob/rel-v2018.2/recipes-multimedia/gstreamer/gstreamer-vcu-examples/vcu-demo-functions.sh#L107-L123 

 

https://download.blender.org/durian/trailer/

File(MP4) -> decoder -> Display
(source)                (sink)
gst-launch-1.0 filesrc location=sintel_trailer-1080p.mp4 ! qtdemux name=demux demux.video_0 !  h264parse ! omxh264dec ! queue max-size-bytes=0 !  kmssink bus-id=fd4a0000.zynqmp-display fullscreen-overlay=1

 

 

Thanks,
Sandeep
PetaLinux Yocto | Embedded SW Support

---------------------------------------------------------------------------
Don’t forget to Reply, Kudo, and Accept as Solution.
---------------------------------------------------------------------------
0 Kudos
fisherjeff
Observer
Observer
3,275 Views
Registered: ‎09-12-2018

I'm running into this exact problem myself and would love to know how @lrocher got around it. I patched the DTG to generate the right addresses when connected to the LPD AXI master (I could never get the FPD to work correctly) and am still having boot failures. Patch details:

 

diff --git a/axi_vcu/data/axi_vcu.tcl b/axi_vcu/data/axi_vcu.tcl
index 129bedc..3ea1313 100644
--- a/axi_vcu/data/axi_vcu.tcl
+++ b/axi_vcu/data/axi_vcu.tcl
@@ -24,10 +24,15 @@ proc generate {drv_handle} {
     }
     # Generate properties required for vcu node
     set node [gen_peripheral_nodes $drv_handle]
+    set vcu_ip [get_cells -hier $drv_handle]
+    set baseaddr [get_baseaddr $vcu_ip no_prefix]
+
     hsi::utils::add_new_dts_param "${node}" "#address-cells" 2 int
     hsi::utils::add_new_dts_param "${node}" "#size-cells" 2 int
     set tab "\n\t\t\t\t"
-    set reg "0x0 0xa0040000 0x0 0x1000>,$tab<0x0 0xa0041000 0x0 0x1000"
+    set slcr_addr [format "%08x" [expr 0x$baseaddr + 0x40000]]
+    set logicore_addr [format "%08x" [expr 0x$baseaddr + 0x41000]]
+    set reg [format "0x0 0x%s 0x0 0x1000>,$tab<0x0 0x%s 0x0 0x1000" $slcr_addr $logicore_addr]
     set_drv_prop $drv_handle reg $reg int
     set intr_val [get_property CONFIG.interrupts $drv_handle]
     set intr_parent [get_property CONFIG.interrupt-parent $drv_handle]
@@ -48,20 +53,24 @@ proc generate {drv_handle} {
 
     # Generate child encoder
     set ver [get_ipdetails $drv_handle "ver"]
-    set encoder_node [add_or_get_dt_node -l "encoder" -n "al5e@a0000000" -p $node]
+    set encoder_addr [format "%08x" [expr 0x$baseaddr + 0x00000]]
+    set encoder_name [format "al5e@%s" $encoder_addr]
+    set encoder_node [add_or_get_dt_node -l "encoder" -n $encoder_name -p $node]
     set encoder_comp "al,al5e-${ver}"
     set encoder_comp [append encoder_comp " al,al5e"]
     hsi::utils::add_new_dts_param "${encoder_node}" "compatible" $encoder_comp stringlist
-    set encoder_reg "0x0 0xa0000000 0x0 0x10000"
+    set encoder_reg [format "0x0 0x%s 0x0 0x10000" $encoder_addr]
     hsi::utils::add_new_dts_param "${encoder_node}" "reg" $encoder_reg int
     hsi::utils::add_new_dts_param "${encoder_node}" "interrupts" $intr_val int
     hsi::utils::add_new_dts_param "${encoder_node}" "interrupt-parent" $intr_parent reference
     # Fenerate child decoder
-    set decoder_node [add_or_get_dt_node -l "decoder" -n "al5d@a0020000" -p $node]
+    set decoder_addr [format "%08x" [expr 0x$baseaddr + 0x020000]]
+    set decoder_name [format "al5d@%s" $decoder_addr]
+    set decoder_node [add_or_get_dt_node -l "decoder" -n $decoder_name -p $node]
     set decoder_comp "al,al5d-${ver}"
     set decoder_comp [append decoder_comp " al,al5d"]
     hsi::utils::add_new_dts_param "${decoder_node}" "compatible" $decoder_comp stringlist
-    set decoder_reg "0x0 0xa0020000 0x0 0x10000"
+    set decoder_reg [format "0x0 0x%s 0x0 0x10000" $decoder_addr]
     hsi::utils::add_new_dts_param "${decoder_node}" "reg" $decoder_reg int
     hsi::utils::add_new_dts_param "${decoder_node}" "interrupts" $intr_val int
     hsi::utils::add_new_dts_param "${decoder_node}" "interrupt-parent" $intr_parent reference 

Generated pl.dtsi output:

 

vcu_core: vcu@80100000 {
	#address-cells = <2>;
	#size-cells = <2>;
	clock-names = "pll_ref", "aclk";
	clocks = <&clk 73>, <&clk 71>;
	compatible = "xlnx,vcu-1.1", "xlnx,vcu";
	interrupt-names = "vcu_host_interrupt";
	interrupt-parent = <&gic>;
	interrupts = <0 91 4>;
	ranges ;
	reg = <0x0 0x80140000 0x0 0x1000>,
		<0x0 0x80141000 0x0 0x1000>;
	reg-names = "vcu_slcr", "logicore";
	encoder: al5e@80100000 {
		compatible = "al,al5e-1.1", "al,al5e";
		interrupt-parent = <&gic>;
		interrupts = <0 91 4>;
		reg = <0x0 0x80100000 0x0 0x10000>;
	};
	decoder: al5d@80120000 {
		compatible = "al,al5d-1.1", "al,al5d";
		interrupt-parent = <&gic>;
		interrupts = <0 91 4>;
		reg = <0x0 0x80120000 0x0 0x10000>;
	};
};

Specifically, the xlnx_vcu and allegro modules load correctly but I cannot load either al5d or al5e. It appears that the initialization goes along just fine until it comes to the following line (al_codec.c:189):

 

al5_writel(codec->icache->dma_handle >> 32, AXI_ADDR_OFFSET_IP);

At that point, the kernel hangs and never recovers. If I try manually reading that address (0x80109208 in my case), I see the same result.

 

I've been banging my head against this problem for quite some time now and am running out of time... Any suggestions whatsoever would be GREATLY appreciated.

0 Kudos
rosesjy
Visitor
Visitor
3,148 Views
Registered: ‎07-10-2018
i find that the interrupt num in the fsbl is 32 bigger than the interrupt num in the device tree,do you know why?
0 Kudos
lyleg
Observer
Observer
2,585 Views
Registered: ‎08-09-2018

Does anyone know if the DTG has been fixed in 2018.3 toolset + 2018.3 VCU TRD?

0 Kudos
fisherjeff
Observer
Observer
2,280 Views
Registered: ‎09-12-2018
0 Kudos