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rdemara
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Registered: ‎05-29-2015

xapp1082 location of patch file?

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I'm setting up eth1 as ps emio example (A) from http://www.wiki.xilinx.com/Zynq+PL+Ethernet. I've set up the hardware design for the picozed (I ported it) and I'm confident that the VHDL code is in fact doing what it is supposed to. I'm currently runnning peta-linux 2015.4. In the directions (3.5.3) it says to apply the patch:

git am $XAPP_HOME/software/patch/0001-ethernet-xilinx-Add-XAPP1082-support.patch

 

This file is not located anywhere in the xapp1082 zip file from Xilinx. I'm having an issue where the driver is looking for "aper_clk" which I believe is incorrect and this patch should fix, upon kernel boot:

xemacps e000c000.ethernet: aper_clk clock not found.
xemacps: probe of e000c000.ethernet failed with error -2

 

Device tree:

 

        slcr: slcr@f8000000 {
            #address-cells = <1>;
            #size-cells = <1>;
            compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
            reg = <0xF8000000 0x1000>;
            ranges;
            clkc: clkc@100 {
                #clock-cells = <1>;
                compatible = "xlnx,ps7-clkc";
                fclk-enable = <0xf>;
                clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
                        "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
                        "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
                        "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
                        "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
                        "dma", "usb0_aper", "usb1_aper", "gem0_aper",
                        "gem1_aper", "sdio0_aper", "sdio1_aper",
                        "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
                        "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
                        "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
                        "dbg_trc", "dbg_apb";
                reg = <0x100 0x100>;
            };

            pinctrl0: pinctrl@700 {
                compatible = "xlnx,pinctrl-zynq";
                reg = <0x700 0x200>;
                syscon = <&slcr>;
            };
        };

 

&gem1 {
   #address-cells = <1>;
   #size-cells = <0>;
    clocks = <&clkc 14>, <&clkc 31>;
    clock-names = "gem1", "gem1_aper";
   compatible = "xlnx,ps7-ethernet-1.00.a";
   /*enet-reset = <&ps7_gpio_0 11 0>;*/
   enet-reset = <&gpio0>;
   interrupt-parent = <&intc>;
   interrupts = <0 22 4>;
   local-mac-address = [00 0a 35 00 1e 54];
   reg = <0xe000c000 0x1000>;
   xlnx,eth-mode = <0x1>;
   xlnx,has-mdio = <0x0>;
   xlnx,ptp-enet-clock = <111111115>;

   phy-handle = <&phy1>;
   phy-mode = "rgmii-id";
    phy1: phy@6 {
        compatible = "Xilinx PCS/PMA PHY";
        device_type = "ethernet-phy";
        xlnx,phy-type = <5>;
        reg = <6>;
    };
};

 

It looks like the current version of the driver xilinx_xemacps.c is looking for "aper_clk" and "ref_clk" instead of "gem1" and "gem1_aper" so it fails to load.

 

Any thoughts?

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rdemara
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Registered: ‎05-29-2015

 


ethernet@e000b000 { /*Copper RJ-45 to eth0*/ compatible = "cdns,gem"; reg = <0xe000b000 0x1000>; status = "okay"; interrupts = <0x0 0x16 0x4>; clocks = <0x1 0x1e 0x1 0x1e 0x1 0xd>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <0x1>; #size-cells = <0x0>; phy-mode = "rgmii-id"; xlnx,ptp-enet-clock = <0x69f6bcb>; local-mac-address = [00 0a 35 00 1e 53]; phy-handle = <0x4>; mdio { status = "disabled"; }; phy@0 { compatible = "marvell,88e1510"; device_type = "ethernet-phy"; reg = <0x0>; marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>; linux,phandle = <0x4>; phandle = <0x4>; }; }; ethernet@e000c000 { /*SFP+ - Fiber to eth1*/ compatible = "cdns,gem"; reg = <0xe000c000 0x1000>; status = "okay"; interrupts = <0x0 0x2d 0x4>; clocks = <0x1 0x1f 0x1 0x1f 0x1 0xe>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <0x1>; #size-cells = <0x0>; phy-mode = "rgmii-id"; xlnx,ptp-enet-clock = <0x69f6bcb>; local-mac-address = [00 0a 35 00 1e 54]; phy-handle = <0x5>; phy@6 { compatible = "Xilinx PCS/PMA PHY"; device_type = "ethernet-phy"; xlnx,phy-type = <0x5>; reg = <0x6>; linux,phandle = <0x5>; phandle = <0x5>; }; };

Relevant Device tree for our design above. We used Section 3 from: http://www.wiki.xilinx.com/x2.%20XAPP1082%20v%204.0-3.%20XAPP1082%20v3.0 to set of the PL side. We route SFP+ to the PS eth1 through EMIO.

 

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rdemara
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Registered: ‎05-29-2015
Follow up... Do I need to use the xilinx_emacps driver for eth1 of the zynq? Can I use the same one used for eth0, "cdns,gem"?
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rdemara
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Registered: ‎05-29-2015
I figured out my issue and had a general misunderstanding of how clicking works and he differences between kernels. Looks like Xilinx switched over to the cadence macb driver and the xilinx_xemac driver is no longer used. I'll post my device-tree later on for anyone it may help.
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rdemara
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Registered: ‎05-29-2015

 


ethernet@e000b000 { /*Copper RJ-45 to eth0*/ compatible = "cdns,gem"; reg = <0xe000b000 0x1000>; status = "okay"; interrupts = <0x0 0x16 0x4>; clocks = <0x1 0x1e 0x1 0x1e 0x1 0xd>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <0x1>; #size-cells = <0x0>; phy-mode = "rgmii-id"; xlnx,ptp-enet-clock = <0x69f6bcb>; local-mac-address = [00 0a 35 00 1e 53]; phy-handle = <0x4>; mdio { status = "disabled"; }; phy@0 { compatible = "marvell,88e1510"; device_type = "ethernet-phy"; reg = <0x0>; marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>; linux,phandle = <0x4>; phandle = <0x4>; }; }; ethernet@e000c000 { /*SFP+ - Fiber to eth1*/ compatible = "cdns,gem"; reg = <0xe000c000 0x1000>; status = "okay"; interrupts = <0x0 0x2d 0x4>; clocks = <0x1 0x1f 0x1 0x1f 0x1 0xe>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <0x1>; #size-cells = <0x0>; phy-mode = "rgmii-id"; xlnx,ptp-enet-clock = <0x69f6bcb>; local-mac-address = [00 0a 35 00 1e 54]; phy-handle = <0x5>; phy@6 { compatible = "Xilinx PCS/PMA PHY"; device_type = "ethernet-phy"; xlnx,phy-type = <0x5>; reg = <0x6>; linux,phandle = <0x5>; phandle = <0x5>; }; };

Relevant Device tree for our design above. We used Section 3 from: http://www.wiki.xilinx.com/x2.%20XAPP1082%20v%204.0-3.%20XAPP1082%20v3.0 to set of the PL side. We route SFP+ to the PS eth1 through EMIO.

 

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