11-06-2012 04:02 PM
I am able to build and insmod the xfifo-dma.ko example driver per the instructions in the
The addresses are correclly read from the device tree as can be seen from the diagnostics printed when I load the driver.
When I try the test "dd if=/dev/urandom bs=2048 count=1 of=/dev/fifo-dma0"
I receive a fault "DMA fault type 0x20000 at address 0x2e196021 on channel 1"
the PL300 documentation indicates the 0x20000 bit is data write error.
The /proc/driver/xfifl_dma status shows the correct number of opens and writes but 0 bytes written. This is correct due to the faults.
Any thoughts on what would cause this?
03-07-2013 05:05 PM
You've gotten a little bit farther than I have.
When I try to start the DMA with the dd command, it just hangs on me.
I can control-C out of it, though.
Do you happen to know how one would invoke this DMA in actual source code ? The example gives a file operation that can be given from a command line, however, what I'm really interested in is performing writes and reads to the PL from a application.
03-07-2013 05:11 PM
The PL330 is probably not what you want for general reads and writes to PL peripherals from a user application. To simplify the process of creating a driver under Linux you might want to look into using either /dev/mem or UIO wrappers.
03-07-2013 06:18 PM
Oh, why is that?
DMAs free up the processor so I can do other stuff.
Do you not think the DMA engine is worthy of transferring this way?
/dev/mem method, you mean mapping the address to virtual space and using processor to to the reading?
I eagerly await your response, as the dma sounded like a good option.
03-07-2013 06:19 PM
Rob, what I'm interested in doing is moving stuff from a device in PL (A fifo) into a DDR buffer somewhere.
If you know of a good way to do this that doesn't drag down the processor too much and is not too slow, you could help me out a lot.
03-08-2013 09:15 AM - edited 03-08-2013 09:22 AM
I don't mean that the PL330 isn't a good DMA engine, just that there are a lot of other options out there as well. There's some overhead that goes into configuring the PL330 it that goes beyond what you'd find in a less programmable DMA engine and you would probably have to write a driver for it yourself - the driver that I put up on the Wiki site is really just an example. It's not really a general-purpose implementation, so outside of its specific application (transferring blocks of data to the AXI MM2S FIFO core) you'd have to modify it on your own.
There are a few other options that you might want to look into, including the AXI Central DMA, AXI Video DMA, etc. depending on the specifics of what you're trying to do. Those can bolt directly onto the HP ports in the PS block giving you direct, high-bandwidth access to DDR from the PL.
Depending on your level of comfort with HDL coding, you could even build a (very) lightweight AXI master interface and connect it to the HP port yourself, depending on the complexity of your use case.
03-08-2013 10:04 AM
I appreciate the response. It does seem somehwat involved to set up a transfer.
I will look into the AXI DMA and other cores that could be set up in the PL.
My main concern was on the SW side, working in a Linux environment, what would be the easiest, most efficient way to get data from PL to DDR where PS can access it, without having to deal with the whole driver aspect of it.
03-18-2013 11:09 AM
The information in pdev comes from either the DTS file or the platform configuration structure. For Zynq, most (if not all) of the platform configuration is done via the DTS file these days.
The AXI DMA driver works differently from the PL330 DMA, but to be honest I haven't had the opportunity to use it much yet so unfortunately I don't have much guidance to offer here. One of the other members of the forum may have more experience with it.
04-15-2013 04:44 PM
It sounds like you want to do exactly what I need to do, get a lot of data from the PL to the PS or PS to the PL efficiently, without burdening the CPU. I don't think the PL330 has been fully tested and I haven't heard of anyone successfully using it. I have searched....
I have spent way too much time trying to get it to work. I have been able to get it to "almost" work, except that the wrong number of bytes acually get transfered. Program the DMAC to xfer 100 bytes and 105 actually get written!! Further, you can't create and setup the dma channel from wihtin in an ISR. A read_dma() routine that works when called from normal driver space can't be called from an ISR. Go figure.
I have a driver implementation limping along currently using the CPU to read out of the FIFO word by word. It is incredibly ineffient and we can't seem to get any guidance from Xilinx or their support on the best way to do this. This is incredible since one would think this very thing the zynq would be used for.
Let me know if you find a reasonable solution.
07-02-2013 04:21 AM
I'm looking for exactly the same. I need to transfer data from the PS to the PL and back, preferably through a FIFO in the PL. But it is very unclear what is the best way to implement this.
07-30-2013 07:03 AM
This (and other very similar) thread/s have been on for several months and the moment questions about drivers appear, well, questions are all that seem to appear from then on. Is anyone at Xilinx even reading these and listening to customers? Because this isn't Stack Overflow where people do users a favor. We paid for these products and demand some support for that money.
If we are going to spend two months on setting this platform up before useful work can begin, this is a serious fail on Xilinx's part.
Here's a really good product/SoC... oh by the by, you'll need a few months before you can use it so make sure you tell the guys that fund you to take that extra time into account... it's on us.
07-30-2013 09:27 AM
I am afraid we could never get the PL330 DMA working. As far as I can tell there are no actual working examples available and no one has ever made the statement that they successfully implemented a PL330 driver. (Someone must have though since it is listed in the /proc/interrrups catalog...) I agree this is a Xilinx deficiency...
Anyway, we saw no successful end in sight for the PL330 driver so we shifted gears to use the AXI DMA IP Core (6.03) and are nearing completion with that. We are using it in simple mode (not scatter gather). Note that we were forced to put a FIFO in front of the DMA Core as the core would drop a packet at the beginning of the PL->PS transfer.
I hope this helps.