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Contributor
Contributor
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Registered: ‎02-20-2016

xilinx_devcfg.c driver got deprecated in 2018.1 release

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Hi!

I'd like to know why xilinx_devcfg.c driver for Zynq-7000 is got deprecated in 2018.1 release? We've developed software framework for our custom board with Zynq-7000 and have used xilinx_devcfg.c driver there. The new Zynq PL programming solution (using FPGA Manager) breaks the compatibility with releases pre-2018.1 and later! Will any support for xilinx_devcfg.c driver be added in future releases?

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Xilinx Employee
Xilinx Employee
2,385 Views
Registered: ‎01-21-2008

Yes, This is supported from xilfpga library in 2018.2 and will be full Partial Reconfiguration bitstream loading support from 2018.3

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Xilinx Employee
Xilinx Employee
2,764 Views
Registered: ‎01-21-2008

Hi miloserdin,


Yes, we have deprecated xilinx_devcfg as Linux moved to FPGA Manager framework. So older and newer Zynq devices are supported to FPGA Manager. there won't be any support for xilinx_devcfg s/w library.

 

Do let us know what is not working for you?

 

With the FPGA Manager we have below support is available & Coming soon:=> 

 

1. In 2018.1 - FPGA_MANAGER - support Standalone & Linux OS (kernel configuration) for PL bit-stream configuration & reconfiguration (No Partial Reconfiguration support & No readback PL configuration support)

2. In 2018.2 - FPGA_MANAGER - support Standalone & Linux OS (kernel configuration) for PL bit-stream configuration & reconfiguration  with PL configuration register read-back (No Partial Reconfiguration support & No readback PL configuration support)

3. In 2018.3 - FPGA_MANAGER - support Standalone & Linux OS (kernel configuration) for PL bit-stream configuration & reconfiguration, with Partial Reconfiguration and Readback PL configuration supported.

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Moderator
Moderator
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Registered: ‎06-27-2017

@miloserdin,

 

To add more information, Below driver is for zynq fpga manager support and few code is borrowed from xdevcfg driver.

drivers/fpga/zynq-fpga.c

Attached commit patch has added support for FPGA manager for zynq. It may useful for your framework.

 

Regards
Kranthi
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Kranthi
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Contributor
Contributor
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Registered: ‎02-20-2016

Thanks for the information!

I tried to load bitstream file (.bit) to Zynq-7000 PL using FPGA manager and got the following error:

"Invalid bitstream, could not find a sync word. Bitstream must be a byte swapped .bin file".

Why do you drop support for full bitstream files with header (.bit) which are generated by Vivado by default? The legacy xilinx_devcfg.c driver has support for them and has byte-swapped routine included.

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Mentor
Mentor
2,705 Views
Registered: ‎06-10-2008

Several years ago the devcfg driver also only supported the stupid bin file format. But it matured and got to support the bit files as generated by Vivado. Are you really telling us that we are back at square one? Is this an attempt to p*** your customers off?

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Contributor
Contributor
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Registered: ‎02-20-2016

Yes, as for now Zynq and ZynqMP PL programming solution (via FPGA manager) offered by Xilinx in 2018.1/2 releases supports only binary bitstream file with byte-swapped data (not a bit file generated by Vivado by default)!

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Xilinx Employee
Xilinx Employee
2,656 Views
Registered: ‎01-21-2008

@miloserdin

 

Yes the FPGA bitstream need to be procesed thrgough the BOOTGEN s/w to get the Bit swapped bitstream to use for PCAP/FPGA Manager to configure correctly.

 

Have a look wiki link http://www.wiki.xilinx.com/FPGA+Manager+ZCU102 

 

Also FPGA Manager accept the .BIN file format only. To Build the bin file, Create a BIF file using any ASCII TEXT editor with below template.  Say for example file "boot_a53_bin_pl_all.bif" you have generated for BOOTGEN.

 

all:
{
design_1_wrapper.bit
}

 

Create the bin file of the bitstream (from XSCT) by suing BootGEN utility from SDK s/w:

 

$ bootgen -image boot_a53_bin_pl_all.bif -arch zynqmp -process_bitstream bin

 

After above BootGEN command Bin File i.e. "design_1_wrapper.bit.bin" will b generated. Use generated BIN file (design_1_wrapper.bit.bin) for final FPGA Manager configuration.

 

Hope this helps.

 

FYI - See Wiki link at http://www.wiki.xilinx.com/FPGA+Manager+ZCU102

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Contributor
Contributor
2,648 Views
Registered: ‎02-20-2016

Thanks a lot, @jadhavs!

Do you plan to add support for full bitstream files with header (.bit) which are generated by Vivado by default to xilfpga library? Our customers use bitstreams containing PL logic only and need to reload them after boot.

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Xilinx Employee
Xilinx Employee
2,386 Views
Registered: ‎01-21-2008

Yes, This is supported from xilfpga library in 2018.2 and will be full Partial Reconfiguration bitstream loading support from 2018.3

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Moderator
Moderator
2,370 Views
Registered: ‎12-04-2016

Hi @miloserdin

 

If your queries have been answered, kindly mark the appropriate answer post as an accepted solution, that will help others looking for similar answer

 

 

Best Regards

Shabbir

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Mentor
Mentor
1,925 Views
Registered: ‎06-10-2008

@jadhavs wrote:

Yes, This is supported from xilfpga library in 2018.2 and will be full Partial Reconfiguration bitstream loading support from 2018.3


If this is supposed to be supported, then how should it be used? I still get the following error with Petalinux 2018.3:

root@petalinux:~# cp /run/media/mmcblk0p1/system.bit /lib/firmware/
root@petalinux:~# echo system.bit > /sys/class/fpga_manager/fpga0/firmware fpga_manager fpga0: writing system.bit to Xilinx Zynq FPGA Manager fpga_manager fpga0: Invalid bitstream, could not find a sync word. Bitstream must be a byte swapped .bin file fpga_manager fpga0: Error preparing FPGA for writing

I want my Vivado engineer to be able to generate a bitstream file and copy that onto the target and program it. He should not be concerned with installing and running petalinux tools on his Windows machine.

Maarten

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Visitor
Visitor
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Registered: ‎12-10-2018

petalinux2018.3 

root@dky_7045_4_26:/mnt# mkdir -p /lib/firmware

root@dky_7045_4_26:/mnt# echo 1 > /sys/class/fpga_manager/fpga0/flags

root@dky_7045_4_26:/mnt# cp toppr.bit.bin /lib/firmware/

root@dky_7045_4_26:/mnt# echo toppr.bit.bin > /sys/class/fpga_manager/fpga0/firmware

[ 181.805423] fpga_manager fpga0: writing toppr.bit.bin to Xilinx Zynq FPGA Manager

[ 184.332499] fpga_manager fpga0: Error after writing image data to FPGA

-sh: echo: write error: Connection timed out

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Contributor
Contributor
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Registered: ‎02-20-2014

With the removal of the original xilinx_devcfg driver, the support for FCLK export also seems to have gone. :/

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Mentor
Mentor
1,602 Views
Registered: ‎06-10-2008

@jadhavs wrote:

Yes, This is supported from xilfpga library in 2018.2 and will be full Partial Reconfiguration bitstream loading support from 2018.3


And now we have petalinux 2019.1 and still this is not fixed. It was silently documented on the wiki but not added to this forum thread:


Missing Features, Known Issues and Limitations

  • No support for partial Bitstream loading.
  • No support for Authenticated and Encrypted Bitstream loading.
  • It is capable of loading only .bin format files into PL. It does not support any other file format.

Again I wonder: is this a way to scare people away from Zynq towards the more expensive ZynqMP?

And in the meantime, Vivado 2019.1 also cannot directly generate .bin files and neither can one run bootgen on the Zynq itself.

Can anyone tell why the FPGA manager is preferred over the old xdevcfg driver? I have yet to see the first advantage.

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Visitor
Visitor
1,423 Views
Registered: ‎05-24-2019

We are also very disapointed about the loss of xilinx_devcfg.c driver.  Our company has develop products using the various Zynq-7000 boards. Our software and ".bit"/".bin" files (for configuring PL) are store on an SD-card.  The boards boot linux from flash and execute "init.sh" from the SD card.  "init.sh" runs our software and the software programs the PL.  So it is easy for our customers to up date their systems.  Also, our software programs the PL at various time depending on the function required.  All that said.  The "xilinx_devcfg.c drive" functionality has been very useful to us and it loss is a hard pill to swallow.  Why not keep that functionality (which was very simple and useful) and include the other.  At least provide the same functionality.  The "cat file.xxx > /dev/xdevcfg" method for programming the PL from software under linux was so simple, I don't know how it could be improved.  Is there any hope of getting that back?