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Adventurer
Adventurer
9,928 Views
Registered: ‎06-05-2014

xylon drm fails to get pixel clock

i'm in the process of porting the ZC702 TRD to a different board that doesn't have the si570 clock so i'm trying to use the logiclk ip core. When I boot I get these messages

 

[ 0.947037] [drm:xylon_drm_crtc_create] *ERROR* failed get pixel clock
[ 0.953502] [drm:xylon_drm_load] *ERROR* failed create xylon crtc

 

I have the logiclk core hooked up and using the clk0_drp output going to the logicvc vclk input. The logiclk seems to be ok

 

[ 1.241677] logiclk 43c50000.clock-generator: precise output frequency 75000000 Hz

 

Has anyone else played with these combinations of cores?

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9 Replies
Xilinx Employee
Xilinx Employee
9,882 Views
Registered: ‎08-01-2008

Re: xylon drm fails to get pixel clock

check this TRD
http://www.wiki.xilinx.com/Zynq+Base+TRD+2014.2
I am not sure if its helps
Thanks and Regards
Balkrishan
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Observer xylonsupport
Observer
9,842 Views
Registered: ‎05-14-2013

Re: xylon drm fails to get pixel clock

How did you set dts "clocks" entry?

Is it set to reference to used logiclk output?

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Observer xylonsupport
Observer
9,827 Views
Registered: ‎05-14-2013

Re: xylon drm fails to get pixel clock

Hi,

 

Xylon ported ZC702 BaseTRD on ZedBoard and this design use logiCLK IP: http://www.logicbricks.com/logicBRICKS/Reference-logicBRICKS-Design/Ported-Xilinx-TRD-to-ZedBoard.aspx

 

Download link: http://www.logicbricks.com/logicBRICKS/Reference-logicBRICKS-Design/Xylon-Reference-Designs-Navigation-Page.aspx

 

Best regards,

Dean

Xylon Support Team

 

Adventurer
Adventurer
9,818 Views
Registered: ‎06-05-2014

Re: xylon drm fails to get pixel clock

thanks. I did start with the ZED reference design I downloaded from your website. Unfortunately the project creation fails right before it hooked up the logiclk. So, I can see much of the design but this key component of the logiclk to the logicvc isn't illustrated.
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Adventurer
Adventurer
9,815 Views
Registered: ‎06-05-2014

Re: xylon drm fails to get pixel clock

well, I didn't so I'm guessing that's a problem ;) Here is what I see in the ready_to_test folder of the ZED reference design for the logicvc entry. I don't see a "clocks". Can you modify to illustrate it's use? Do I just do clocks = <&phandlenameforlogiclk>?

logicvc@40030000 {
compatible = "xylon,logicvc-4.00.a";
reg = <0x40030000 0x10000>;
interrupt-parent = <0x3>;
interrupts = <0x0 0x22 0x4>;
background-layer-bits-per-pixel = <0x20>;
background-layer-type = "rgb";
color-space = <0x1>;
interface = <0x0>;
readable-regs;
size-position;
pixel-stride = <0x800>;
linux,phandle = <0x10>;
phandle = <0x10>;

layer_0 {
bits-per-pixel = <0x20>;
type = "rgb";
transparency = "layer";
};

layer_1 {
bits-per-pixel = <0x10>;
type = "yuv";
transparency = "layer";
};
};
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Observer xylonsupport
Observer
9,795 Views
Registered: ‎05-14-2013

Re: xylon drm fails to get pixel clock

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Highlighted
Observer xylonsupport
Observer
9,794 Views
Registered: ‎05-14-2013

Re: xylon drm fails to get pixel clock

To create/recreate ZED reference design project you must have evaluation license for logiCLK logicBRICKS IP core.

Best regards,
Dean
Xylon Support Team
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Visitor prjeanneret
Visitor
9,522 Views
Registered: ‎05-12-2015

Re: xylon drm fails to get pixel clock

Is there a working example/design of the Xylon DRM working with Linux? All the examples I've found so far are for the XylonFB module (not DRM) which no longer exists in the mainline Linux kernel. 

 

The current Linux-xlnx kernel is 4.0 and that has options for XylonDRM, but the documentation for how to use it is lacking to say the least. A working example (including the dts information) would be really helpful.

 

Paul

 

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Xilinx Employee
Xilinx Employee
9,519 Views
Registered: ‎12-08-2011

Re: xylon drm fails to get pixel clock

Hi Paul,

 

Please take a look at the Zynq Base TRD as an example and reference of how to use the Xylon DRM driver:

http://www.wiki.xilinx.com/Zynq+Base+TRD+2015.2

 

The above design is based on the 2015.2 tool suite and a 3.19 Linux kernel. An updated design for 2015.4 and 4.0 Linux kernel will be released by the end of the year.

 

Hope this helps!

 

Chris

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