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Observer ntrojani
Registered: ‎06-29-2018

zcu102 rev1.1 ethernet problems, whit petalinux 2018.2


i'm work on a zcu102 eval board rev 1.1, i follow all users guide to bring up the board; preprare a QSPI boot image and all working fine. I have try to use ethernet connection defined by gem3 RGMII.

I have a problem after bootstrap; i see continuosly link-up and link-down request operation printed out from the uart-dbg. I run the ping command from pc host and i see some timeout operation (it is like the lost connection)

I have try to search on the forum and try more solution but whitout success.

here is the output command from dmesg | grep 'macb\|phy'

[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] arch_timer: cp15 timer(s) running at 99.99MHz (phys).
[ 1.773889] libphy: Fixed MDIO Bus: probed
[ 1.778017] macb ff0e0000.ethernet: Not enabling partial store and forward
[ 1.778391] libphy: MACB_mii_bus: probed
[ 1.781754] macb ff0e0000.ethernet eth0: Cadence GEM rev 0x50070106 at 0xff0e0000 irq 31 (00:0a:35:00:22:01)
[ 1.781773] TI DP83867 ff0e0000.ethernet-ffffffff:0c: attached PHY driver [TI DP83867] (mii_bus:phy_addr=ff0e0000.ethernet-ffffffff:0c, irq=POLL)
[ 3.621175] xilinx-psgtr fd400000.zynqmp_phy: Lane:1 type:8 protocol:4 pll_locked:yes
[ 4.830706] dwc3-of-simple ff9d0000.usb0: dwc3_simple_set_phydata: Can't find usb3-phy
[ 6.451625] macb ff0e0000.ethernet: gem-ptp-timer ptp clock registered.
[ 35.109512] macb ff0e0000.ethernet eth0: link up (100/Full)
[ 40.229432] macb ff0e0000.ethernet eth0: link down
[ 42.277501] macb ff0e0000.ethernet eth0: link up (100/Full)
[ 46.373436] macb ff0e0000.ethernet eth0: link down
[ 48.421502] macb ff0e0000.ethernet eth0: link up (100/Full)
[ 50.469431] macb ff0e0000.ethernet eth0: link down
[ 52.517494] macb ff0e0000.ethernet eth0: link up (100/Full)
[ 56.613426] macb ff0e0000.ethernet eth0: link down

i dont' understand if  ff0e0000.ethernet-ffffffff:0c is correct ( i mean if the value ethernet-ffffffff is rigth)

here is other information about u-boot gem3 configuration :

Bootmode: QSPI_MODE
Net: ZYNQ GEM: ff0e0000, phyaddr c, interface rgmii-id
eth0: ethernet@ff0e0000
U-BOOT for USCP_zc102

and here is my user-system.dtsi

&gem3 {


     phy-handle = <&phyc>;

     phy-mode = "rgmii-id";

     compatibile = "cdns, zynqmp-gem";

     local-mac-address = [00 0A 35 00 22 01];

     phc: phy@c{

            reg = <0xC>;



            ti, fifo-depth = <0x1>;

            ti, rxctrl-strap-worka;


            phandle= <0x10>;




the design hardware configuration for ethernent controller is :

Configuration mode is RGMII DP83867IRAP by Texas Instrument connected directly to RJ45 connector.

Comunication mode is RMGII and MIO Pin 64 to 75 are connect

and the pin 76 and 77 atr connected to MDIO interface.

what i wrong ?


thank in advance









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3 Replies
Registered: ‎10-14-2013

Re: zcu102 rev1.1 ethernet problems, whit petalinux 2018.2

Hi @ntrojani ,

did you succeed to fix the ethernet problemas? Any hint where the problem existed?

I'm facing this same with a custom board with similar hardware - and guessing that I'm missing propably some clocks at Linux or then device tree configuration problems.

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Observer ntrojani
Registered: ‎06-29-2018

Re: zcu102 rev1.1 ethernet problems, whit petalinux 2018.2

Hello, yes i have fix the problem.

I have checked my device-tree, i using the correct device-tree configuration in the gem's used, i see the same problem again.

So i thinking that.. probably is my ethernet swhitch, where it missing the rigth link-up speed, and then i have changed that device and use a new switch up to 1Gbit link-up and now working well.

The right configuration of device-tree was founded into the wiki of xilinx zcu102 eval board configuration

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Registered: ‎10-14-2013

Re: zcu102 rev1.1 ethernet problems, whit petalinux 2018.2

Found that I had a wrong oscillator assembled on the PCB. Somehow the 25MHz schematic CLK25 net name didn't propagate to a signal when using 33MHz crystal! ;)

Also didn't realize that huge amount of clock related frequencies are set on the Zynq Processor system block on Vivado Block Diagram.

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