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svenssonjoel
Contributor
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Registered: ‎03-17-2016

zynq 7010 and petalinux mysteries

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Hello,

 

I am having some trouble with linux on my platform and I cannot really seem to find the pattern in this. So, posting a question here to see if any of it makes sense to someone.

 

If I create a very basic VIVADO design, that is nothing special implemented on the FPGA at all and go through

these following steps -> I get a working linux.

- petalinux-create --type project --template zynq --name <name>

- petalinux-config --get-hw-description=<path to hdf file in sdk directory>

(I just accept the default settings when menuconfig pops up)

- petalinux-build

- petalinux-package --boot

- petalinux-package --prebuilt --fpga <path to bitstream file>

- petalinux-boot --jtag --prebuilt 3

 

Now linux boots and eventually i reach the login prompt... no problems.

 

If the vivado design contans an AXI GPIO module (one bit connected to an LED, an output), and go through the same steps again the linux boot seemingly hangs after a while. last messages printed being:

 

console [ttyPS0] enabled
bootconsole [earlycon0] disabled

 

For a long time I believed these problems were due to UART settings and for some reason linux at this point switching and using "the wrong uart" or something like that. But that is not the pattern I am observing. I have repeated the experiment several times: no AXI-GPIO on the fpga -> linux boots, put it in -> linux does not boot.

 

If any ideas pop up about this, please let me know. 

Thank you

 

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svenssonjoel
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Registered: ‎03-17-2016

Ok! found a solution. It is also mentioned here: https://forums.xilinx.com/t5/Embedded-Linux/WARNING-Will-not-program-bitstream-on-the-target/td-p/565510

 

So the "petalinux-package --prebuilt --fpga <path to bitstream file>" copies the bitstream into  pre-built/linux/implementation but it does not rename it with the name expected. Renaming design1_wrapper.bit to download.bit and it all falls into place. Linux boots.

 

Thanks for the help!

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stephenm
Xilinx Employee
Xilinx Employee
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Registered: ‎09-12-2007

I think there is a mismatch in the HW and the kernel/DTB images. I think the axi gpio is getting probed, but there is no matching HW so, it is failing..

 

You can check this quick, by stopping in uboot, and doing a register read (md 0x<base addr>) on the axi gpio base address. If this fails, then this is the issue and you need to make sure that the correct bitstream is used in the petalinux-package.

gudishak
Moderator
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Registered: ‎06-27-2017

Hi @svenssonjoel,

 

Can you mention the version of Xilinx tools you are trying? 

Are you observing same in SD boot?

 

Best Regards
Kranthi
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gudishak
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Registered: ‎06-27-2017
Can you try running ps7_post_config after sourcing ps7_init.tcl from XSCT shell and then boot?
Best Regards
Kranthi
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svenssonjoel
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Registered: ‎03-17-2016

Thanks @stephenm,

 

That is a great, practical and conrete tip. And you are right the bitstream does not get programmed onto the fpga. It seems that the command "petalinux-package --prebuilt --fpga <path to bitstream file> has failed in doing what I thought it would do.

 

Do you see what part of the petalinux flow that I am mistaken about here? What should I do instead?

 

Thanks a lot.

 

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svenssonjoel
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Registered: ‎03-17-2016

Hello @gudishak,

 

I use the 2017.4 version of Vivado "webpack".

 

 

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svenssonjoel
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1,654 Views
Registered: ‎03-17-2016

Ok! found a solution. It is also mentioned here: https://forums.xilinx.com/t5/Embedded-Linux/WARNING-Will-not-program-bitstream-on-the-target/td-p/565510

 

So the "petalinux-package --prebuilt --fpga <path to bitstream file>" copies the bitstream into  pre-built/linux/implementation but it does not rename it with the name expected. Renaming design1_wrapper.bit to download.bit and it all falls into place. Linux boots.

 

Thanks for the help!

View solution in original post

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