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stroumpf
Visitor
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Registered: ‎10-11-2012

zynq - second ethernet interface missing parent clock

Hi,

 

I'm trying to use the second ethernet interface and it's failed because of inappropriate clock setup with following message

Set GEM clk to -22 Hz

 

Looking somewhat in the code, I see that __clk_round_rate return an inappropriate value as the there is no clk->parent.

 

unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
{
	unsigned long parent_rate = 0;

	if (!clk)
		return -EINVAL;

	if (!clk->ops->round_rate) {
		if (clk->flags & CLK_SET_RATE_PARENT)
			return __clk_round_rate(clk->parent, rate);
		else
			return clk->rate;
	}

	if (clk->parent)
		parent_rate = clk->parent->rate;
	else {
		printk (KERN_NOTICE "%s(), no parent !\n", __FUNCTION__);
	}

	return clk->ops->round_rate(clk->hw, rate, &parent_rate);
}

 

But the parent_clk is set in drivers/clk/zynq/clk.c 

 

Currently looking for some help to understand what going on !  Is there somewhere a special flag to fully enable GEM1 ?

 

regards

David

 

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