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Adventurer
Adventurer
7,156 Views
Registered: ‎09-05-2007

zynq ultrascale+ MPSoc uio /dev/mem access

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Dear all

 

is there something special regarding UIO access on zynqmp ?

I can access my IP in standalone code

but I can't use the same design in linux (petalinux2017.1)

mmap return an address that cause a fault when accessed :

unhandled level 1 translation fault (11) at 0xffffff81bce00c

 

should I use mmap64 ? unsigned long int *ptr ?

can I safely assume that xipname_linux.c wrapper code generated by vivado_hls 2017.1 are correct ?

 

regards

raph

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Adventurer
Adventurer
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Registered: ‎09-05-2007
Issue in vivado hls C wrapper. Address type is hardcoded as u32 instead of void* device descriptor

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Xilinx Employee
Xilinx Employee
7,116 Views
Registered: ‎10-06-2016

Hi @raphael.ponsard

 

Can you share your application code to see how are you accessing to the IP?


Ibai
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Adventurer
Adventurer
7,101 Views
Registered: ‎09-05-2007

Thank you for your assistance...

I am using vivado and petalinux 2017.1, and zcu102 ES2

 

linux code is : (same standalone code -with XPAR_ADDITION_1_DEVICE_ID in place of "addition" is running ok)

 

 

XAddition xa;
printf("XAddition_Initialize\n");
XAddition_Initialize(&xa,"addition");
printf("base address %x",xa.Bus_a_BaseAddress); printf("XAddition_Write_a_Words\n"); XAddition_Write_a_Bytes(&xa,0,t1,N*4); //access fault ERROR here

output is :

 

 

 

XAddition_Initialize
base address b7a11000
XAddition_Write_a_Words
accessing address b7a11100
[   64.048922] x_hlsadder.elf[1542]: unhandled level 1 translation fault (11) at 0xb7a11100, esr 0x92000045
[   64.063045] pgd = ffffffc0746b1000
[   64.066409] [b7a11100] *pgd=0000000000000000[   64.070480] , *pud=0000000000000000
[   64.073955]
[   64.075431]
[   64.076904] CPU: 0 PID: 1542 Comm: x_hlsadder.elf Not tainted 4.9.0-xilinx-v2017

IMHO plnx-aarch64-system.dts is correct :

root@plnx_aarch64:~# cat /sys/class/uio/uio0/name
addition

root@plnx_aarch64:~# cat /proc/device-tree/amba_pl\@0/addition\@a0000000/compatible
xlnx,addition-1.0generic-uio

 

addition@a0000000 {
			compatible = "xlnx,addition-1.0", "generic-uio";
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x59 0x4>;
			reg = <0x0 0xa0000000 0x0 0x10000>;
			xlnx,s-axi-bus-a-addr-width = <0xb>;
			xlnx,s-axi-bus-a-data-width = <0x20>;
		};

any ideas    ?

 

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Adventurer
Adventurer
7,093 Views
Registered: ‎09-05-2007

same issue with gpio access with /dev/mem

 

#define GPIO_BASE_ADDRESS     	0x00A0020000
#define GPIO_DATA_OFFSET     	8   //led on gpio channel 2
#define GPIO_DIRECTION_OFFSET   12  //idem
#define MAP_SIZE 4096UL
#define MAP_MASK (MAP_SIZE - 1)

int main()
{
    int memfd;
    volatile unsigned int  *mapped_base;
    volatile unsigned int  *dev_base = (volatile unsigned int  *)GPIO_BASE_ADDRESS;
    printf("gpio access through mmap v0.0.4\n\r");
    memfd = open("/dev/mem", O_RDWR | O_SYNC);
    mapped_base = (volatile unsigned int *)mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, memfd, (__off_t) dev_base );
    printf("Mem address %p.\n", mapped_base);
    printf("ddr address %p.\n", (unsigned  int *)((unsigned int)mapped_base + GPIO_DIRECTION_OFFSET));
    *((volatile unsigned int *) ((unsigned  int)mapped_base + GPIO_DIRECTION_OFFSET)) = 0;

access fault :

./xgpio.elf
gpio access through mmap v0.0.4
Mem address 0x7f982d9000.
ddr address 0x982d900c.

[  690.448153] xgpio.elf[1565]: unhandled level 1 translation fault (11) at 0x982d900c, esr 0x92000045
[  690.457286] pgd = ffffffc075b30000
[  690.460653] [982d900c] *pgd=0000000000000000[  690.464722] , *pud=0000000000000000
[

 

 

but design and dts are ok :

 

root@plnx_aarch64:~# ls /sys/class/gpio/
export       gpiochip322/ gpiochip496/ gpiochip504/ unexport     
root@plnx_aarch64:~# echo 496 > /sys/class/gpio/export 
root@plnx_aarch64:~# echo out > /sys/class/gpio/gpio496/direction 
root@plnx_aarch64:~# echo 0 > /sys/class/gpio/gpio496/value 
led0 turn OFF
root@plnx_aarch64:~# echo 1 > /sys/class/gpio/gpio496/value 
led0 turn ON
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-06-2016

Hi @raphael.ponsard

 

If I'm not wrong your issue might be related to the data type widths, as pointers in aarch64 are 64bit width an in one of the operation you are converting to 32bit.

 

printf("ddr address %p.\n", (unsigned  int *)((unsigned int)mapped_base + GPIO_DIRECTION_OFFSET));
*((volatile unsigned int *) ((unsigned  int)mapped_base + GPIO_DIRECTION_OFFSET)) = 0;

If you need to do peration with the pointers do not convert them to 32 bit.


Ibai
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Adventurer
Adventurer
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Registered: ‎09-05-2007

 

actually I was hacking around this issue too

I did made the first tests with unsigned long int pointer that cause the same fault

 

 

I am here because I have the same issue with uio driver code generated by vivado_hls2017.1 

I did assume that xipname_linux.c has wrapper for 64 bis address

 

 

I will double check

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Xilinx Employee
Xilinx Employee
7,037 Views
Registered: ‎10-06-2016

Hi @raphael.ponsard

 

I also realized that the DTS node that you posted does not match with the address that you used in the linux example, is it right the right address?

 

addition@a0000000 {
			compatible = "xlnx,addition-1.0", "generic-uio";
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x59 0x4>;
			reg = <0x0 0xa0000000 0x0 0x10000>;
			xlnx,s-axi-bus-a-addr-width = <0xb>;
			xlnx,s-axi-bus-a-data-width = <0x20>;
		}

 

#define GPIO_BASE_ADDRESS     	0x00A0020000

Ibai
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Adventurer
Adventurer
7,026 Views
Registered: ‎09-05-2007
0x00a0000000 is HLS addition IP addr
0x00A0020000 for gpio (leds) addr
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Adventurer
Adventurer
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Registered: ‎09-05-2007
Issue in vivado hls C wrapper. Address type is hardcoded as u32 instead of void* device descriptor

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Observer
Observer
4,063 Views
Registered: ‎11-06-2017

What would be the correct way to mitigate it when using mmap()?

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Visitor
Visitor
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Registered: ‎04-11-2018

One way is to not use the aarch64 compiler but instead use the 32 bit compiler, like arm-linux-gnueabi-gcc  :)

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