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lim.junhyoung
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Registered: ‎03-27-2019

zynqmp and marvell dsa 88e6320

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i using zynqmp 


I am trying to use marvell's 88e6320 which is an ethernet switch device.

I have seen several community resources in this regard. The data I saw is as follows.

https://forums.xilinx.com/t5/Embedded-Linux/zynq-and-marvell-dsa-88e6352-integration-device-tree/td-p/779400

https://forums.xilinx.com/t5/Embedded-Linux/Problem-with-Marvell-88E6320-connected-to-GEM3-in-ZynqMP/td-p/902612

But that didn't solve it. What should I do?


And there are additional questions.

Where can I find the address of mdio when I write it?

In the mdio data at the address below,

https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/net/mdio.txt

I think that the reg property of the mdio is determined by the mido address in the device tree. But I don't know what mdio's address is.

 

my system-user.dtsi 

/ {
chosen {
bootargs = "console=ttyPS0,921600n8 earlycon clk_ignore_unused cpuidle.off=1 uio_pdrv_genirq.of_id=generic-uio";
};

newmdio0: mdio0 {
compatible = "cdns,macb-mdio";
reg = <0xe000b000 0x1000>;
clocks = <&clk 30>, <&clk 30>, <&clk 13>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
};
};

#size-cells = <0>;

switch0: switch0@0 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;

dsa,member = <0 0>;

ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
};

port@1 {
reg = <1>;
label = "lan1";
};

port@2 {
reg = <2>;
label = "lan2";
};

port@3 {
reg = <3>;
label = "lan3";
};

switch0phy5: port@5 {
reg = <15>;
label = "cpu";
ethernet = <&gem1>;
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};

&gem1 {
phy-mode = "rgmii-id";
status = "okay";
phy-handle = <&switch0phy5>;
};

 

my uboot error

ZYNQ GEM: ff0c0000, phyaddr 5, interface rgmii-id
mdio_register: non unique device name 'eth0'
ZYNQ GEM: ff0c0000, phyaddr 5, interface rgmii-id
mdio_register: non unique device name 'eth0'
ZYNQ GEM: ff0c0000, phyaddr 5, interface rgmii-id
mdio_register: non unique device name 'eth0'
ZYNQ GEM: ff0c0000, phyaddr 5, interface rgmii-id
mdio_register: non unique device name 'eth0'
No ethernet found.
ZYNQ GEM: ff0c0000, phyaddr 5, interface rgmii-id
mdio_register: non unique device name 'eth0'
Hit any key to stop autoboot: 0

 

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shabbirk
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Registered: ‎12-04-2016

Hi @lim.junhyoung 

As communicated earlier, we dont have the support for this particular chip in u-boot. You can refer to u-boot drivers/net/phy to see the list of PHY drivers being supported in u-boot.

For your reference, I am seeing some relevant links upon searching in google, which I think might be helpful to add the support by yourself

https://translate.google.com/translate?hl=en&sl=zh-CN&u=http://javaquan.com/post/18903_1_1.html&prev=search

 

NOTE: We dont oficially support this PHY switch

 

 

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shabbirk
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Registered: ‎12-04-2016

Hi @lim.junhyoung 

It seems to me that the device tree is incorrect, as I cant see the newmdio label being not defined in your device tree file. Can you just compare the device tree against the device tree outlined in this solution post of the below forum link

https://forums.xilinx.com/t5/Embedded-Linux/Problem-with-Marvell-88E6320-connected-to-GEM3-in-ZynqMP/td-p/902612

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lim.junhyoung
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Registered: ‎03-27-2019

 

Hi. @shabbirk 

 

As I wrote in the text, I already checked the link. When the device tree was constructed like the link, I wrote it as

/include/ "system-conf.dtsi"
/ {
        chosen {
        bootargs = "console=ttyPS0,921600n8 earlycon clk_ignore_unused cpuidle.off=1 uio_pdrv_genirq.of_id=generic-uio";
        };
        mdio1: mdio0 {
            compatible = "cdns,macb-mdio";
            reg = <0x0 0xff0c0000 0x0 0x1000>;
            clock-names = "pclk", "hclk", "tx_clk", "rx_clk";
            clocks = <0x3 0x1f 0x3 0x34 0x3 0x30 0x3 0x34>;
            #address-cells = <1>;
            #size-cells = <0>;
        };
};

&gem1 {
  phy-handle = <&switch0cpu5>;
};

&mdio1 {
   switch0: switch0 {
    compatible = "marvell,mv88e6085";
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0>;
    status = "okay";
    dsa,member = <0 0>;

     ports {
         #address-cells = <1>;
        #size-cells = <0>;
        port@3 {
            reg = <3>;
            label = "lan0";
            };

        switch0cpu5: port@5 {
            reg = <0>;
            label = "cpu";
            ethernet = <&gem1>;
            phy-mode = "rgmii-id";
            fixed-link {
                    speed = <1000>;
                    full-duplex;
                };
            };
        };
    };
};

However, after booting Linux, it links up but does not communicate with the PC.

Also, after setting ip through 'setenv ipaddr' command in uboot, if you try to ping with pc, it will reboot. The log message for this is as follows:

## Error: flags type check failure for "serverip" <= "AUTO" (type: i)
himport_r: can't insert "serverip=AUTO" into hash table
In:    serial@ff000000
Out:   serial@ff000000
Err:   serial@ff000000
Board: Xilinx ZynqMP
Bootmode: NAND_MODE
Net:   ZYNQ GEM: ff0c0000, phyaddr 0, interface rgmii-id
PHY is not detected
GEM PHY init failed
No ethernet found.
U-BOOT for sw

ZYNQ GEM: ff0c0000, phyaddr 0, interface rgmii-id
mdio_register: non unique device name 'eth0'
ZYNQ GEM: ff0c0000, phyaddr 0, interface rgmii-id
mdio_register: non unique device name 'eth0'
ZYNQ GEM: ff0c0000, phyaddr 0, interface rgmii-id
mdio_register: non unique device name 'eth0'
ZYNQ GEM: ff0c0000, phyaddr 0, interface rgmii-id
mdio_register: non unique device name 'eth0'
No ethernet found.
ZYNQ GEM: ff0c0000, phyaddr 0, interface rgmii-id
mdio_register: non unique device name 'eth0'
Hit any key to stop autoboot:  0
ZynqMP> setenv ipaddr 12.12.12.15
ZynqMP> ping 12.12.12.13
ZYNQ GEM: ff0c0000, phyaddr 0, interface rgmii-id
mdio_register: non unique device name 'eth0'
ZYNQ GEM: ff0c0000, phyaddr 0, interface rgmii-id
mdio_register: non unique device name 'eth0'
ZYNQ GEM: ff0c0000, phyaddr 0, interface rgmii-id
Insufficient RAM for page table: 0x15000 > 0x14000. Please increase the size in get_page_table_
resetting ...
Xilinx Zynq MP First Stage Boot Loader
Release 2018.2   Aug 19 2019  -  13:39:43
Manufacturer: MICRON      MT29F4G08ABAFAWP    ,
Device Model: MT29F4G08ABAFAWP    ,
Jedec ID: 0x2C
Bytes Per Page: 0x1000
Spare Bytes Per Page: 0x100
Pages Per Block: 0x40
Blocks Per LUN: 0x800
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shabbirk
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Registered: ‎12-04-2016

Hi @lim.junhyoung 

Can you check whether PHY support has been enabled in your u-boot?

Try enabling these options after running:

petalinux-config -c u-boot -> Device Drivers -> Ethernet PHY (physical media interface) support ->  Marvell Ethernet PHYs support

petalinux-config -c u-boot -> Device Drivers -> Ethernet PHY (physical media interface) support ->  Marvel MV88E61xx Ethernet switch PHY support 

petalinux-config -c u-boot -> Device Drivers -> Marvell 88E6352 switch support

 

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tmaintz
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Registered: ‎12-26-2016

Hi @lim.junhyoung 

we had the same problem and were not able to get the switch running in U-Boot but in Linux (we even got the same messages with eth0). Please make sure you apply the MACB patch from this post's solution. Your device-tree is the same as ours (what a suprise :) ).

In Linux you can enable your port e.g. lan 1 by

$ ifconfig lan1 192.168.1.69

But you see some messages in the dmesg on startup.

Long story short: In Linux this excellent post leads you to heaven; in U-Boot you won't get far.

Cheers,
Thomas

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lim.junhyoung
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Registered: ‎03-27-2019

@shabbirk 

 

I checked now that u-boot config is not set for the marvell switch you mentioned.

 

petalinux-config -c u-boot -> Device Drivers -> Ethernet PHY (physical media interface) support ->  Marvel MV88E61xx Ethernet switch PHY support 

 

When I run the above command, I see a new yield of cpu port, bitmask of phy ports, and bitmask of phyless serdes ports. How do I set this?

 

i set 

cpu port (5)

bitmask of phy ports (0x1F)

bitamask of phyless serdes ports(0)

 

but same issue

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lim.junhyoung
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Registered: ‎03-27-2019

@tmaintz 

I have referred to all the links you have already given me.

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shabbirk
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Registered: ‎12-04-2016

Hi @lim.junhyoung 

I am suspecting that this particular PHY switch support (88e6320) is not available in u-boot. 

By any chance, did you try booting to linux and see if this detects there in linux?

 

Best Regards

Shabbir

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lim.junhyoung
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@shabbirk 

my board setup:

zynqmp | mv88e6321
0xff0c0000, GEM1 --- RGMII -- | PORT5 |
PL --- RGMII -- | PORT2 PORT3 -----| --- PC
PL --- RGMII -- | PROT6 |

vivado design

image.png



I don't care about ethernet between the marvell switch and the PL, and now I only want to communicate with the PC connected port3 on the marvell switch and GEM1 on the PS.

After booting linux, it will link up and show the eth0 device.

But it doesn't communicate with the pc.

Below is my kernel message.
The fix in the kernel is that rgmii-id seems to need rx, tx delay, so I added the enable code. If boot from the original source without adding this code, the result is the same.

kernel message

[ 3.691644] udevd[1732]: starting version 3.2.2
[ 3.696937] udevd[1733]: starting eudev-3.2.2
[ 3.771964] mv88e6085 ff0c0000.mdio0-mii:00: switch 0x3100 detected: Marvell 88E6321, revision 2
[ 3.944866] libphy: mv88e6xxx SMI: probed
[ 3.945451] DSA: switch 0 0 parsed
[ 3.945878] DSA: tree 0 parsed
[ 3.946457] mv88e6xxx_port_set_rgmii_delay::53
[ 3.947062] mv88e6xxx_port_set_rgmii_delay::58 mode[0]
[ 3.983718] mv88e6xxx_port_set_rgmii_delay::53
[ 3.984311] mv88e6xxx_port_set_rgmii_delay::58 mode[9]
[ 3.984951] mv88e6xxx_port_set_rgmii_delay::79
[ 3.985550] mv88e6xxx_port_set_rgmii_delay::84 p0 : delay RXCLK yes, TXCLK yes
[ 4.062621] Marvell 88E6390 mv88e6xxx-0:03: attached PHY driver [Marvell 88E6390] (mii_bus:phy_addr=mv88e6xxx-0:03, irq=POLL)
Starting internet superserver: inetd.
Configuring packages on first boot....
(This may take several minutes. Please do not power off the machine.
Running postinst /etc/rpm-postinsts/100-sysvinit-inittab...
update-rc.d: /etc/init.d/run-postinsts exists during rc.d purge (cont
Removing any system startup links for run-postinsts ...
/etc/rcS.d/S99run-postinsts
INIT: Entering runlevel: 5
Configuring network interfaces... [ 4.485139] Generic PHY fixed-0: :phy_addr=fixed-0:00, irq=POLL)
[ 4.487654] pps pps0: new PPS source ptp0
[ 4.488163] macb ff0c0000.ethernet: gem-ptp-timer ptp clock regist
[ 4.489063] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
udhcpc (v1.24.1) started
Sending discover...
[ 5.502473] macb ff0c0000.ethernet eth0: link up (1000/Full)
[ 5.503200] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes read
[ 6.878600] PLL: shutdown
Sending discover...
Sending discover...
No lease, forking to background

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shabbirk
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Registered: ‎12-04-2016

Hi @lim.junhyoung 

You mean in Linux, you are not able to ping to or communicate with PC, as I can see link is detected in linux.

Any specific reason why you are testing the eth phy functionality in uboot?

Best Regards

Shabbir

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lim.junhyoung
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Registered: ‎03-27-2019

@shabbirk 

I am uploading BOOT.BIN file to nand frequently because I am working on board bring up now. In order to do this, uboot must be enabled for ethernet to download the BOOT.BIN file.

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shabbirk
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Registered: ‎12-04-2016

Hi @lim.junhyoung 

I can only see the below PHY switch support in u-boot source code. You can go through this source and modify according to your requirements for 88e6320 switch.

https://github.com/siemens/u-boot/blob/master/drivers/net/phy/mv88e6352.c

 

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lim.junhyoung
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@shabbirk 

Do you mean that I need to look at the link source for my marvell switch and add a new source to uboot?

Is there a way to write BOOT.BIN to nand via ethernet after linux boot?

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gudishak
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Registered: ‎06-27-2017

Hi @lim.junhyoung 

 

You can use below command to write file to nand flash in Linux. Is that you are looking for? 

nandwrite -p /dev/mtdX <file>

 

Best Regards
Kranthi
--------------------------
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lim.junhyoung
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Hi. @gudishak 

 

thank you!

do you know uboot source about mavell switch 88e68321 ?

 

 

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shabbirk
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Registered: ‎12-04-2016

Hi @lim.junhyoung 

As communicated earlier, we dont have the support for this particular chip in u-boot. You can refer to u-boot drivers/net/phy to see the list of PHY drivers being supported in u-boot.

For your reference, I am seeing some relevant links upon searching in google, which I think might be helpful to add the support by yourself

https://translate.google.com/translate?hl=en&sl=zh-CN&u=http://javaquan.com/post/18903_1_1.html&prev=search

 

NOTE: We dont oficially support this PHY switch

 

 

View solution in original post

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lim.junhyoung
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@gudishak

thank you
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