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Adventurer
Adventurer
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Registered: ‎03-22-2016

zynqmp_dma hangs after 1 burst

I'm writing a kernel module to communicate with an AXI4-Stream-FIFO block. I have the module working completely using individual calls to iowrite32() or iowrite64() in both AXI-Lite and AXI4 modes, with data widths of 32 and 64.

 

I'm now trying to convert over to using DMA to get higher throughput. I was able to leverage the zynqmp_dma driver in the kernel to use the built-in DMA engines of the zynq, and I have read and write transfers working - but only for sizes up to a single burst. That is to say, I can send/recv any size up to 32 64-bit words without issue.

 

In Analyzer, this appears as WREADY going high, WVALID going high for 16 sets of 2 clocks (2 64-bit words at a time), for a total of 32 64-bit words), ending with WREADY going low and WLAST going high for a clock.

 

Anything over 32 words appears the same. WREADY still drops at the 32nd word, WLAST still goes high to mark the end of the burst, but the DMA never completes.

 

If I understand it right, 16 is the maximum burst size, so I believe it should be sending out multiple bursts back-to-back until the transfer is complete. That is not happening, however, and I am out of ideas for debugging.

 

Has anyone done this type of work using the zynqmp_dma DMA driver? Any suggestions are welcome, thanks!

 

Image 1: DMA transfer of 16 words

Image 2: DMA transfer of 32 words

Image 3: DMA transfer of 33 words

Image 4: Non-DMA transfer of 2 words

dma_16_word.png
dma_32_word.png
dma_33_word.png
nodma_2_word.png
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