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Observer n.horvat
Observer
239 Views
Registered: ‎02-19-2018

AMM Master Bridge - PS_PL Interface

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Hello,

is it possible to gain access to the PS (Zynq US+ MPSoc) DDR Controller from "AMM Master Birdge" IP Core which is placed in PL?

When I connect "M_AXI" port from "AMM Master Bridge" IP Core to the "HP FPD" port on the PS (Zynq US+ MPSoc), "HP FPD" port stays unconnected slave in Vivado Address Editor (option "Auto Assign Address" remains greyed out).

Attached are two images. One image represent my design block diagram and other address editor information.

Thank you.

.amm_master_bridge_to_ps_Diagram.PNG

amm_master_bridge_to_ps_Address_Editor.PNG

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Xilinx Employee
Xilinx Employee
148 Views
Registered: ‎02-01-2008

Re: AMM Master Bridge - PS_PL Interface

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IP Packager should also have a section that allows you to assign the address range (region) for your axi master interface. In your address tab, I don't see M_AXI as a master to address the ranges within the HP port.

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Xilinx Employee
Xilinx Employee
195 Views
Registered: ‎09-01-2014

Re: AMM Master Bridge - PS_PL Interface

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This is because you don’t connect the avalon_s0 interface. please make it connected or external.
Observer n.horvat
Observer
174 Views
Registered: ‎02-19-2018

Re: AMM Master Bridge - PS_PL Interface

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I can confirm that address mapping is working while making avalon interfaces external and connecting them mannualy in hdl wrapper file.

This is ok as a workaround but I will like to have this working while making direct connection in Block Design.

I packed my avalon IP core with Vivado IP Packager and I used "Auto Infer Interface Chooser" to infer avalon signals from my IP core (check image bellow).

Is there any additional settings in Vivado IP Packager that need to be taken care of while packing a IP with avalon interface?

 

avalon_to_axi.PNG
amm_master_bridge_to_ps_Address_Editor.PNG
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Xilinx Employee
Xilinx Employee
149 Views
Registered: ‎02-01-2008

Re: AMM Master Bridge - PS_PL Interface

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IP Packager should also have a section that allows you to assign the address range (region) for your axi master interface. In your address tab, I don't see M_AXI as a master to address the ranges within the HP port.

Observer n.horvat
Observer
132 Views
Registered: ‎02-19-2018

Re: AMM Master Bridge - PS_PL Interface

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Thanks for both answers! Finnaly, after IP core instantiation in Block Design, interface can be successfully mapped in Address Editor.

For those who might face similar issue:

First, in Vivado IP Packager, under "Ports and Interfaces" section, create a desired interface (it was avalon master interface in my case). Then under "Addressing and Memory" section, execute "Addressing and Memory Map Wizard". After wizard completes, specify "Range" and "Width" of the created address space. Package your IP.

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Contributor
Contributor
119 Views
Registered: ‎07-18-2018

Re: AMM Master Bridge - PS_PL Interface

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Hi

Can you tell me how to add 

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