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Observer n.horvat
Registered: ‎02-19-2018

AMM Slave Bridge - BSP Poblem


my custom IP core consist of two AXI4LITE Slave interfaces. In Vivado, after connecting them to the AXI master (eg. ZYNQ), they are both visible in Address Editor with assigned addresses.

In "system.hdf" file both of my slave peripherals are recognized, but after generation of BSP, only one axi peripheral is visible in "xparameters.h" file.

I can access both of them from cpu but there is no "BASEADDR" constant defined in "xparameters.h" file for second axi slave peripheral.

Is this known issue with Xilinx SDK (limitation?) or is there some kind of setting that need to be set while packing the IP core?

(I'm using Vivado 2018.2)

Thank you.


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