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Registered: ‎07-19-2012

AXI Lite Custom Address decoding, behavioral simulation works while post synthesis functional is broken

Hi all,



Does anyone have any tips on finding why a behavioral simulation runs correctly while a post synthesis functional simulation fails? I'm using the Vivado simulator. Here's some backround.


I'd like to ask some veterans for advice. After developing a custom AXI Lite slave peripheral I noticed that there seems to be a problem with my custom address decoding. Returning to the project I developed the customized IP in and running a post synthesis functional simulation the problem with the address decoder manifested itself. So my task is to find out why the behavioral simulation runs fine while the post synthesis simulation fails. I think using the scope in the post synthesis functional simulation is a good tool to find the difference between the pre and post synthesis simulations but I'm finding it difficult to make that much sense out of the file that my verilog has been converted to. 


I've tried to.. hack, for lack of a better term, the AXI Lite slave peripheral generated using the IP wizard with my custom BRAM controller code from a virtex 4 design.  I did this to try to stay within the paradigm of the way the address decoding is done in the auto generated code, I'm considering just starting from scratch and doing the decoding my own way unless anyone has some advice.


I would use the AXI BRAM controller in the library but I want to write to one port with the fabric and read from the other port using the processor. 


Thanks, I appreciate all replys 




...maybe I'll start a blog...


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Registered: ‎07-19-2012

Re: AXI Lite Custom Address decoding, behavioral simulation works while post synthesis functional is broken

I suspect my problem is a simple issue with how I'm handling this. I havn't inclded any code, I'll try my hand at fixing this and post my code if I have any more issues





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