10-20-2017 02:15 PM
I have a DMA that connects to Zynq HP port through AXI mem interconnect in 64bit mode. Because the length of each transfer can be anything from 1 to 16 in length. I could only generate address write at the end of each burst. However, upon the first WValid assertion, WReady never comes up. Based on the TRM page 130, WReady on the HP_slave side is only affected by FIFO full in 64bit mode. And this is the case when I probe the WReady on the HP side.
So why is the AXI interconnect blocking my transfer? I thought the address channel and data channel should be independent based on AXI specification. Adding register slice and/or data fifo doesn't help. I also tried AXI protocol converter with various options and it still blocks my transfer.
10-23-2017 02:24 AM
I have some queries to answer your question:
1. Did you execute FSBL before DMA starts any transfer to PS?
2. Is DMA a custom IP, or from Vivado catalog?
10-23-2017 01:50 PM
The DMA is a customized one aimed to reduce LUT/Flop usage and improve performance. I'm running AXI_HP at 200MHz.
I didn't execute FSBL before running the program. It's usually fine with my old DMA design which generate address handshake before data/wvalid is latched. Plus, I've probed the AXI between my DMA and AXI_mem_interconnect using ILA. I'm pretty certain it's AXI_mem_interconnect blocking my transfer.
Current I've made a workaround by generating address when data is available and setting awlen at maximum. If last data is encountered, my DMA would stop reading upstream FIFO and finish the burst by stuffing dummy write.
Now I observed that there's at least four cycles of waiting between address handshake and WReady pulling high. This is still a huge performance loss. (20% at awlen = 15) I trade it off by increasing awlen. But on the other hand, dummy write would cause more waiting. I would still like to know the inner working of AXI interconnect if you have more information.