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Adventurer
Adventurer
3,887 Views
Registered: ‎11-04-2009

AXI master connected to axi_7series_ddrx (based on AR37425)

(Xilinx EDK 14.3) (Virtex 7 VC707)

 

Dear all,

 

I would like to connect a customIP AXI master to axi_7series_ddrx in order to burst data to external memory. The final goal is

 

1) to deserialize ADC data in my customIP (I have done this in a ISE project and tested using Chipscope) 

2) Do some processing depending on my application

3) Burst data to external memory

4) Use hw interrupts from my IP in order Microblaze read data from memory and send them to a PC via Ethernet

 

Question

---------------

Can i use AR37425 in order to create my AXI master customIP or this template is to be used only for EDK 12.3? Is the create peripheral wizard the only solution (adding master support) using EDK 14.3?

 

I'd prefer not to use the peripheral Wizard but write my own AXI master custom IP, like NPI Interface example in previous PLB based systems.

 

Thus, i tried AR37425 which has an example in verilog for AXI master custom IP.

 

The problem is that DDR3 seems to not respond as i see in Chipscope. I have checked that init_calibration signal is asserted before trying to burst data in memory. I used exactly the code of Xilinx answer.

 

Any recommendations? Have anyone done something similar?

 

Thank you in advance,

 

Lefteris

 

 

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