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Contributor
Contributor
10,291 Views
Registered: ‎04-09-2015

AXI4 Interconnect Clock Conversion

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Hi everyone,

 

I am currently trying to figure out how the clock conversion within the AXI Interconnect (v1.06a) works.

 

I have two clock domains, a 100MHz domain for the user design and a 200 MHz domain for MIG and Interconnect. So MIG and Interconnect run at 200MHz and the user-design runs at 100MHz. 200MHz and 100MHz are derived from the same PLL.

 

Unbenannt.png

 

Now when I configure the Interconnect through Core Generator (ISE 14.4) there is an option for the clock conversion, namely the "Is Aclk Async" and the "AXI Aclk Ratio".

Unbenannt2.png

 

1. My expectation: I thought setting one of those two settings automatically converts the 100MHz user-design AXI-Interface Signals into the 200MHz MIG AXI-Interface Signals and backwards so I don't have to worry about clock conversion here, as per this diagram from ds768:

Unbenannt3.png

 

1. Question: Am I correct in the sense that I would need to set the "AXI Aclk Ratio" to 1:2 in my specific case?

 

1. Problem: Because that somehow didn't work as I thought it would.

 

1. Explanation: There are 4 channels, 2 write- and 2 read-channels. Read-requests go through the AXI Interconnect, but only the first 2-3 write-request come through and then no further write-requests go through the AXi Interconnect. The WREADY Signals don't assert anymore at the Interconnect SI-Interface. It does at the MIG! Which means the Interconnect must be the tricky part.

I even tried to set the "Is Aclk Async" which inserts those Data-FIFOs between the SI- and MI-Hemisphere (as far as my understanding goes from ds768, pg059, wp417, xapp789). That helped a bit in the sense that 1-3 more write-request go through before the AXI Interconnect shuts down the write lanes again.

 

1. Annotation: If i leave the whole design (user-design + Interconnect + MIG) within the same clock domain (200MHz) then it works perfectly fine.

 

Anyone can help me or pinpoint me into the right direction where to search for a possible solution?

 

Cheers,

Steffen

 

 

 

 

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1 Solution

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Contributor
Contributor
18,559 Views
Registered: ‎04-09-2015

Re: AXI4 Interconnect Clock Conversion

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Hi everyone,

 

final update:

Well, guys, if anyone ever has this sort of problem, guess what ... check your constraints first!

And talking about basics. If you copy constraints from an ip-core into your design, always make sure that your adjustments to these constraints that you made afterwards get applied as well, because otherwise the main clock contraints might be commented out of your design.

 

At least, I have to admit, for not having any clock contraints the design was working pretty well :D

 

Cheers and solved,

Steffen

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8 Replies
Contributor
Contributor
10,201 Views
Registered: ‎04-09-2015

Re: AXI4 Interconnect Clock Conversion

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Any idea? Anyone?

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Xilinx Employee
Xilinx Employee
10,186 Views
Registered: ‎02-01-2008

Re: AXI4 Interconnect Clock Conversion

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I've never used the core generator version of the interconnect and have only used the IPI version.

 

You have not posted what your acceptance and issuance values are. I presume you have packet fifo enabled. In the IPI version, if you have an async clock and datawidth conversion, then a single clockCrossing-datawidthConverting core will be added to the interconnect. This core uses bram for the clock crossing and datawidth convertion. There are cases where this core will only accept three outstanding requests before it applies backpreasure even if your acceptance values are set to a larger number. In order to get around this issue, I usually place the clock crossing IPI block outside of the interconnect. This way, the clock crossing and datawidth conversion logic is seperated.

 

If you tell the clock crossing block that the clocks are different but sync, (such as 1:2), then logic is used, instead of bram, for the clock crossing but timing may be harder to meet.

 

 

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Contributor
Contributor
10,179 Views
Registered: ‎04-09-2015

Re: AXI4 Interconnect Clock Conversion

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Hey johnmcd,

 

thanks for the reply.

 

I didn't change the acceptance and issuance values. They are all at their default value of 1.

 

I'll post my current values here:

Unbenannt.pngUnbenannt2.pngUnbenannt3.pngUnbenannt34.png

 

Since my acceptance and issuance values are all the same at 1 each channel should get the same amount of access bursts, don't they?

 

Maybe putting the clock-crossing in front of the Interconnect is a good idea, like you mentioned. That would mean, I need an AXI-FIFO, if sth. like that exists. I'll have a look.

 

Cheers,
Steffen

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Contributor
Contributor
10,156 Views
Registered: ‎04-09-2015

Re: AXI4 Interconnect Clock Conversion

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The AXI-FIFO approach doesn't seem to work like I thought it would.

Let's say I have an Interconnect like I mentioned above (2-write-only-paths and 2 read-only-paths).

In case of a write-only path the user-design writes data into the FIFO, but there needs to be some management that writes the data from the FIFO to the Interconnect. The FIFO itself doesn't automatically offer its data to the write-only-port of the interconnect.

Vice versa for a read-only-path.

 

So this approach doesn't work.

 

I am still trying different configurations, if I get somewhere, I'll let you know.

 

Any other ideas? Anyone?

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Contributor
Contributor
10,098 Views
Registered: ‎04-09-2015

Re: AXI4 Interconnect Clock Conversion

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Hey everyone,

 

just to keep you updated.

 

Since the Interconnect clock conversion doesn't seem to work (or I maybe simply have a wrong understanding of its functionality), I am implementing the clock crossing myself.

 

Cheers,

Steffen

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Contributor
Contributor
10,010 Views
Registered: ‎04-09-2015

Re: AXI4 Interconnect Clock Conversion

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Hi everyone,

 

another update.

 

Implemented clock-crossing myself, which is working now.

 

One problem still persists:

After successful 1-9 write/read-operations with successful data-transfer one of the four channels always becomes drowned. I mean by that, the interconnect doesn't serve this channel anymore with the appropriate valid/ready signals. The remaining three channels read/write as expected.

 

I am currently trying to play around with the acceptance-values.

Is this the right direction to go from here or am I on the wrong track?

 

Cheers,

Steffen

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Contributor
Contributor
18,560 Views
Registered: ‎04-09-2015

Re: AXI4 Interconnect Clock Conversion

Jump to solution

Hi everyone,

 

final update:

Well, guys, if anyone ever has this sort of problem, guess what ... check your constraints first!

And talking about basics. If you copy constraints from an ip-core into your design, always make sure that your adjustments to these constraints that you made afterwards get applied as well, because otherwise the main clock contraints might be commented out of your design.

 

At least, I have to admit, for not having any clock contraints the design was working pretty well :D

 

Cheers and solved,

Steffen

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Observer kafka
Observer
3,429 Views
Registered: ‎07-04-2011

Re: AXI4 Interconnect Clock Conversion

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Hi,

 

I have the similar situation. I would like to have mig component with AXI working at 200Mhz  and two AXI masters with 100MHz. I created the appropriate ict106_axi_interconnect component but it is not working neither with 1:2 nor async ratio. I looked deep into the ISIM simulation and it looks like for example C_REG_CONFIG parameter from some point is not passed correctly in simulator. It was set to bypass so some signals at 100Mhz domain lasted only half of period (I checked slice registers).

 

On the other hand when I used async it also appeared that C_S_AXI_IS_ACLK_ASYNC was not properly passed...

 

How did you overcome this issue? I mean did you succeeded in using this component with different clock ratios?

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