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Visitor andreadicola
Visitor
340 Views
Registered: ‎01-09-2019

AXI4 Peripheral with Memory and Registers

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Hi all,

I am working with Vivado 2018.2 on an AC701 board.

I am trying to implement an AXI4 Peripheral to be interfaced with MicroBlaze.

The question I have is the following: is it possible to create an AXI4 Peripheral with both memories and registers?

At the moment what I can see from the "Create and Package New IP" wizard in the "Add Interface" page is that if I choose a "Lite" interface I can have Registers (I can choose the number) but not a Memory, while if I choose a "Full" interface I can have a Memory (I can choose the size) but not Registers.

Am I wrong in understanding something?

Thank you in advance.

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1 Solution

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Xilinx Employee
Xilinx Employee
279 Views
Registered: ‎01-09-2019

Re: AXI4 Peripheral with Memory and Registers

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Hello @andreadicola ,

So AXI Lite and AXI Full are interfaces with addresses assigned in memory so that you can configure them.  In AXI Lite you have a certain number of registers in the default template which allows you to configure a custom IP using these registers.  In the AXI Full template IP code, there are BRAM blocks instantiated giving that block the ability to hold data on its own, seperate from the PS.

To your original question, I don't believe you can have both in one IP core, or if that would be necessary.  Likely you will want to work with an AXI Lite Custom IP, as AXI Lite has less signals to think about with common features between the two.

Thanks,

Caleb

Thanks,
Caleb
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Xilinx Employee
Xilinx Employee
280 Views
Registered: ‎01-09-2019

Re: AXI4 Peripheral with Memory and Registers

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Hello @andreadicola ,

So AXI Lite and AXI Full are interfaces with addresses assigned in memory so that you can configure them.  In AXI Lite you have a certain number of registers in the default template which allows you to configure a custom IP using these registers.  In the AXI Full template IP code, there are BRAM blocks instantiated giving that block the ability to hold data on its own, seperate from the PS.

To your original question, I don't believe you can have both in one IP core, or if that would be necessary.  Likely you will want to work with an AXI Lite Custom IP, as AXI Lite has less signals to think about with common features between the two.

Thanks,

Caleb

Thanks,
Caleb
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Scholar dgisselq
Scholar
269 Views
Registered: ‎05-21-2015

Re: AXI4 Peripheral with Memory and Registers

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@andreadicola,

I'm going to go out on a limb here and declare that yes, you can have both in one core.

You might have a bit of a nightmare building it though.

In general, block RAM takes one cycle to read.  Yes, Xilinx offers a distributed RAM that does not, but let's suppose you need one cycle to read from your memory.  You'll also need a second cycle to select between having read a register and a having read from memory.

To build this into an AXI peripheral, you're going to have to carefully consider the back pressure (i.e. !BREADY or !RREADY) and work that backwards through your core.  The pipeline control is not going to be trivial--especially not if you want to be able to read and write on adjacent time-slots.

Dan

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Explorer
Explorer
262 Views
Registered: ‎12-11-2017

Re: AXI4 Peripheral with Memory and Registers

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The main difference between Full and Lite is that Full supports block transfers while Lite does not. Lite is also limited to 32 bits usually, though 64 is allowed.

You can use an AXI Interconnect block to hook up your Lite stuff and BRAM to the Microblaze. The toolchain infers the port type and insert the appropriate conversions as needed on each downstream port.

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