We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Registered: ‎03-22-2016

AXI4 Stream Broadcaster width incorrect?

In Block Design of Vivado 2017.1, I add a block for "AXI4 Stream Broadcaster". By default the input stream port has a TDATA width of 8, the two output ports each have a width of 16. I would have expected them to be the same.


When I manually specify TDATA width for SI and MI to be 1, the slave TDATA width is properly set to 8, but the master TDATA width remains at 16. It seems that the master TDATA width is always exactly twice what I set it to be. As such, "auto" doesn't work, because it's doubling the stream width from the input to the output.


Am I misunderstanding how this block is supposed to work? I'm relatively new to design, but I can't find anything to indicate that the input and output should be anything other than equal widths, unless manually specified.

0 Kudos
1 Reply
Observer tommy_hu
Registered: ‎02-12-2017

Re: AXI4 Stream Broadcaster width incorrect?

I encounter the same issue with AXI4_Stream_Broadcaster, looks like it's an old issue that xilinx didin't fix.


But I see someone successfully use this IP in his project, so there must be a way to fix it manually.

0 Kudos