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Visitor nemmo0
Visitor
11,448 Views
Registered: ‎08-09-2014

AXI4-Stream Switch usage

Hi,

 

I am trying to use an AXI4-Stream Switch with two slave and one master interfaces in my design. In the customization parameter you can set the tdata with in bytes. However if the slave interfaces are chosen to be N bytes in width the master interface automatically becomes N/2 bytes. Why is this? My purpose is to combine packets of data from two AXI Stream slaves  (packet boundary indicated by the TLAST signal) into one AXIS Stream. Isn't AXI4 Stream switch the right ip to use?

Capture.PNG

Thanks

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7 Replies
Community Manager
Community Manager
11,423 Views
Registered: ‎06-14-2012

Re: AXI4-Stream Switch usage

slave _tdata = master_tdata * number of slaves and 
master_tdata = slave_tdata * number of masters

 

tdata[15:0] -> slave0, tdata[31:16] -> slave1, ... and so on.

 

I would suggest to check the HDL to have a better understanding. This is correct.

 

Regards

Sikta

 

 

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Visitor nemmo0
Visitor
11,411 Views
Registered: ‎08-09-2014

Re: AXI4-Stream Switch usage

Hi,

 

I think you mean

 

slave_tdata_width = tdata_width_in_bytes * number of slaves 
master_tdata_width = tdata_width_in_bytes  * number of masters

 

So if you have an N:M switch and tdata_width_in_bytes is configured to X you have slave tdata widths of N*X bytes and masters of M*X bytes.

 

My understanding from a switch is that it connects slave stream to a master stream. So I would expect the slave and master data widths to be equal. I can say that I dont have a full understanding of how this core works and could not find a clear description in the product guide either in the first look. 

 

Where can I find the HDL you mentioned?

 

Thanks

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Scholar sampatd
Scholar
11,402 Views
Registered: ‎09-05-2011

Re: AXI4-Stream Switch usage

You will find the HDL in
C:\Xilinx\Vivado\2014.2\data\ip\xilinx\axis_switch_v1_1\hdl\verilog
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Community Manager
Community Manager
11,394 Views
Registered: ‎06-14-2012

Re: AXI4-Stream Switch usage

Hi 

You can find the HDL accoridng to your IP configuration once you have generated the output products.

For ex: C:\debug_flows\project_2\project_2.srcs\sources_1\bd\design_1\ip\design_1_xbar_0\synth

 

This will be the wrapper file accoring to your IP configuration. The source will be in the src folder for the particular IP.

You have to look at both these files to understand how your parameters are getting translated.

 

Regards

Sikta

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Visitor nemmo0
Visitor
11,386 Views
Registered: ‎08-09-2014

Re: AXI4-Stream Switch usage

thanks

 

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Adventurer
Adventurer
5,971 Views
Registered: ‎05-11-2010

Re: AXI4-Stream Switch usage

Let me see if I understood this right because it seems rather confusing:

 

According to PG085 (tables 2-5 and 2-6), IPs have one separate signal per master/slave interface with a certain width for each AXI signal, with a name like snn_axis_signal, where nn is the interface number.  Therefore, according to the documentation, the ports should be as follows:

  • S00_AXIS
    • s00_axis_tdata[31:0]
    • s00_axis_tvalid
    • s00_axis_tready
  • S01_AXIS
    • s01_axis_tdata[31:0]
    • s01_axis_tvalid
    • s01_axis_tready

However, this seems not to be the case, and instead IPs use a shared signal for all the master/slave interfaces:

  • S00_AXIS
    • s_axis_tdata[31:0]    (lower half of s_axis_tdata[63:0])
    • s_axis_tvalid[0]    (lower bit of s_axis_tvalid[1:0])
    • s_axis_tready[0]    (lower bit of s_axis_ready[1:0])
  • S01_AXIS
    • s_axis_tdata[63:32]    (upper half of s_axis_tdata[63:0])
    • s_axis_tvalid[1]    (upper bit of s_axis_tvalid[1:0])
    • s_axis_tready[1]    (upper bit of s_axis_ready[1:0])

To further confuse things, these indexes are not displayed in Vivado as I wrote them (at least in 2015.4), but instead the whole range is displayed, leading users to think that they are actually different signals:

  • S00_AXIS
    • s_axis_tdata[63:0]    (only bits 31:0)
    • s_axis_tvalid[1:0]    (only bit 0)
    • s_axis_tready[1:0]    (only bit 0)
  • S01_AXIS
    • s_axis_tdata[63:0]    (only bits 63:32)
    • s_axis_tvalid[1:0]    (only bit 1)
    • s_axis_tready[1:0]    (only bit 1)

(The fact that they have the same name could have been because they reflect the name within the bus rather than the IP port, or at least that was my first impression.)

 

In short, the way these signals are displayed is counter-intuitive and is wrongly documented.

 

PS: I just noticed that clicking the s_axis_tdata under S01_AXIS highlights the s_axis_tdata under S00_AXIS rather than the one I clicked, which is more proof that these are actually the same port.

Explorer
Explorer
634 Views
Registered: ‎10-12-2018

Re: AXI4-Stream Switch usage

Yes, this is a bug in the GUI.

All slave and master ports is same width, just in HDL all slave ports merged to one. Which cause that you get one slave ports count times wider dataport.

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