UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer alexafi
Observer
24,909 Views
Registered: ‎11-13-2012

Accessing DDR from PL on Zynq

Jump to solution
Hi everyone, I have a module, synthesized by Vivado HLS, with a AXI master interface. It just copies an array from one location to another. It works well when connected to a BRAM controller, but fails to read/write data from DDR. I referred to the CDMA design in UG873, chapter 6. To access the DDR it just connects its AXI master port to the high-performance AXI slave ports of the PS. I tried connecting my module to these ports, to the ACP and to the general-purpose AXI slave ports with no luck. Am I missing some setting? What could be the reason? Please help me, I will appreciate any hints. My thesis is due in a couple of weeks and I really need to get it working. Thank you! Alex
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Observer alexafi
Observer
35,847 Views
Registered: ‎11-13-2012

Re: Accessing DDR from PL on Zynq

Jump to solution

Solved it!

 

To make it work, I set the (AR/AW)CACHE=0x11 and (AR/AW)PROT=0x00. In the CDMA datasheet, these were the recommended values, which I confirmed with ChipScope, when attached to CDMA's master port.

The default values set by VHLS were 0x00 and 0x10 respectively, which is also the case in the last post.

 

Alex

13 Replies
Adventurer
Adventurer
24,880 Views
Registered: ‎05-24-2013

Re: Accessing DDR from PL on Zynq

Jump to solution

Hello Alex,

 

In ZYNQ, you can not access the DDR pins directly. The only way is to use the hardcoded memory controller in PS7. So you can not access it from the PL. What is the problem when you are settin the hardcoded memory controller in PS7?

 

Regards,

Berk

0 Kudos
Observer alexafi
Observer
24,869 Views
Registered: ‎11-13-2012

Re: Accessing DDR from PL on Zynq

Jump to solution

Hi Berk,

 

I am not accesing the DDR directly, but through the AXI slave ports of the PS, just the way it's described in UG873, chapter 6 http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug873_zynq_ctt.pdf

 

But instead of the "axi_cdma" core from the pcore library, I use my own module with a AXI master interface, generated in Xilinx Vivado HLS. I believe the tool synthesises a valid design, since I am able to access the BRAM controller, through a slave AXI.

 

I thought accessing the DDR would be as easy as the BRAM, since both are accessed through a AXI slave interface, but DDR does not work for me.

 

Has someone done a similar design of creating an accelerator, that would access data in DDR?

 

Thank you,

Alex

0 Kudos
Xilinx Employee
Xilinx Employee
24,825 Views
Registered: ‎02-01-2008

Re: Accessing DDR from PL on Zynq

Jump to solution

It should be as easy as accessing a bram controller. Keep in mind that these ports are AXI3 so the burst size is smaller than AXI4.

 

I would suggest that you add chipscope to your design and look at the axi interface from your master and the axi interface between the interconnect and the HP/SGP/ACP port.

 

Also, if you are using xmd to test written values from your master, use the mrd_phy command in order to guarantee that cache isn't getting in the way.

0 Kudos
Visitor since1934
Visitor
24,791 Views
Registered: ‎06-02-2013

Re: Accessing DDR from PL on Zynq

Jump to solution

Hi, all

 

I have a similar problem on xc7z020 board. I have a module with a AHB2.0 master interface. I used LogiCORE IP AHBLite to AXI Bridge v1.00a. I connected my master port to ahblite port, and the AHBLite to AXI Bridge is connected to S_AXI_HP0. I used ChipScope to monitor the M_AXI and S_AXI Port. To accesing DDR3, S_AXI_HP0 alwasys returns "DECERR" with BRESP/RRESP signal.

 

S_AXI.PNG

 

 

I also try to change my AHB2.0 master interface to AXI master interface, and use LogiCORE IP AXI External Master Connector. It also did not work with the same DECERR error.

 

I try to do a CDMA project from UG873, It is work.

I am nor sure it is right that i connected CDMA M_AXI  with External Master Connector S_AXI, and External Master is connect to S_AXI_HP0.  But when i monitor S_AXI_HP0, it also returns DECERR.

 

Does anyone help me? Thanks.

 

 

 

 

 

 

 

0 Kudos
Highlighted
Observer alexafi
Observer
35,848 Views
Registered: ‎11-13-2012

Re: Accessing DDR from PL on Zynq

Jump to solution

Solved it!

 

To make it work, I set the (AR/AW)CACHE=0x11 and (AR/AW)PROT=0x00. In the CDMA datasheet, these were the recommended values, which I confirmed with ChipScope, when attached to CDMA's master port.

The default values set by VHLS were 0x00 and 0x10 respectively, which is also the case in the last post.

 

Alex

Visitor since1934
Visitor
24,715 Views
Registered: ‎06-02-2013

Re: Accessing DDR from PL on Zynq

Jump to solution

 

Hi Alex,

 

  Thank you for response. My module work with AXI Interface now. The bresp signal returns OK.

 

  Some bits of awprot/arprot signals to "ahblite to axi bridage 1.0.a" can not  be controlled from ahblite port. Maybe it can't be work at this version.

0 Kudos
Explorer
Explorer
24,705 Views
Registered: ‎12-05-2012

Re: Accessing DDR from PL on Zynq

Jump to solution
Hello Alex,

Have you made your BRAM BLOCK PORTS EXTERNAL to write or read from VHDL modules??

Regards
Pruthvi
0 Kudos
Visitor babaraw
Visitor
24,480 Views
Registered: ‎06-04-2013

Re: Accessing DDR from PL on Zynq

Jump to solution

Hi All;

           I am trying to write and read back from DDR from PL via AXI_HP slave port on Zedboard. I use the code provided by xilinx for AXI master. In Chipscope I can see the data is written and read back but stragngly I am unable to see the data written by me in memory anywhere. Memory is full of garbage.

I set AWCAHE = 0010 and ARCACHE = 0010. 

Can anyboady suggest me any hint??

Thanks in advance.

 

0 Kudos
Visitor babaraw
Visitor
24,425 Views
Registered: ‎06-04-2013

Re: Accessing DDR from PL on Zynq

Jump to solution

Anybody there??

Thanks

0 Kudos
Observer owen_oh_ya
Observer
7,800 Views
Registered: ‎08-15-2013

Re: Accessing DDR from PL on Zynq

Jump to solution

Hi all,

i have the same situation.

after force cache[3:0]=f and prot[2:0]=0, i still get error data from 0x3000_0000, is there any configuratio i need to modify as well?

thanks!

 

Owen

0 Kudos
Adventurer
Adventurer
6,593 Views
Registered: ‎12-10-2014

Re: Accessing DDR from PL on Zynq

Jump to solution

how do you do this in Vivado? how do you set the (AR/AW)CACHE=0x11 and (AR/AW)PROT=0x00;

I am having the same issue;

 

 

0 Kudos
5,259 Views
Registered: ‎04-08-2016

Re: Accessing DDR from PL on Zynq

Jump to solution

Hi,

Just small correction. It is not 0x11 (binary would be then 8'b00010001)

but 4'b0011 - "Normal Non-cacheable Bufferable"

 

0 Kudos
Visitor mta97e1
Visitor
5,193 Views
Registered: ‎04-29-2016

Re: Accessing DDR from PL on Zynq

Jump to solution

Hi,

 

My custom module with AXI4 interface trying to write to DDR on PS side throught HP0 port. I am using ZC706 board. 

 

cuntom module->AXI interconnect->HP0 port. I am not seeing nay movement of signals in chapscope.

I have initialized the proessor in SDK.

 

I have treid to write to DDR on PL side with the custom moduel and it is working.

custom module -> AXI interconnect -> AXI DDR controller

 

Is there any register Ihave to enable in PS side?

 

Thanks

0 Kudos