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Observer shawayek
Observer
4,298 Views
Registered: ‎12-13-2013

Advice on AXI DMA design needed

Happy new year everyone. 

 

I am using Vivado 2014.3, developing for the ZC702.

 

I have a design that includes an ADC interface in the PL and an axi_DMA (V 7.1) to transfer the samples captured to memory (S2MM). Currently, the software sets up the DMA for a simple transfer, tells the IP in the PL how many samples it wants to capture in memory, and starts the capture. It works well for a single transfer initiated by software.

 

What I would now like to do is to only transfer an n number of samples after a certain external trigger arrives. I am not sure whether the better approach would be to have the DMA make a transfer every time an event occurs (each event compromised of n samples), or to somehow collect a large number of events and transfer them all at once before going to capture more and do another transfer. What is the typical solution to this problem, and are there any resources I can look at? I've read about DMA interrupts and putting the DMA in cyclic mode, but I don't know which is the best approach for me.  

 

I've included my block design to provide some context. 

baa4f752679aee7fa497c5d347047ad8.png
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Xilinx Employee
Xilinx Employee
4,252 Views
Registered: ‎08-02-2011

Re: Advice on AXI DMA design needed

Well you could easily use your external trigger event to throttle the dma (i.e. deassert tvalid). The question is: how much time do you have between the end of 'n samples arriving' and the next trigger event. This is because, in the simplest case, you'll need to write a couple DMA registers to setup the next transfer. If you have time to do this, then just use register-direct mode DMA with interrupts.

 

If you don't have enough time, the situation is a bit more complex and maybe cyclic mode makes more sense.

 

If you provide more details about the behavior of the 'external trigger event' and the incoming samples, maybe we can be more specific.

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