03-15-2018 06:45 AM
Hi, I have added an "axi quad spi" IP to my zynq-7000 running baremetal. TL;DR problem: Even though I configure the axi_quad_spi IP in quad mode, everything is being sent only over Q0 (as in standard mode).
The AXI4 port is connected to the GP0 of the Zynq. I know for sure the AXI4 path works correctly, and that the axi_quad_spi tri-state pins are handled correctly. The settings for the IP are as follow:
After booting, from the Xilinx SDK XSCT console (AXI4 on GP0) I try then to send a msi_enable command to the QSPI flash memory (N25Q128A), which is as follows (base address is on 0x40000000):
mwr 0x40000060 0x1E6 - Disable master transaction and reset RX/TX FIFOs
mwr 0x40000068 0x06 - Write enable command (supported by my memory)
mwr 0x40000070 0xFFFFFFFE - Chip select for the first slave
mwr 0x40000060 0x086 - Enable master transaction
mwr 0x40000070 0xFFFFFFFF - Disable chip select
mwr 0x40000060 0x186 - Disable master transaction
These steps are according to the axi_quad_spi datasheet pg153 , page 99.
I have connected an oscilloscope to all the signals between the FPGA and the QSPI flash, and what I see happening is that the command 0x06 goes in quad mode (2 cycles, 4 bits each cyle), it goes only on Q0 (8 cycles, 1 bit per cycle). So somehow even though the axi_quad_spi IP is configured in Quad mode, it is sending the data in standard mode. The QSPI flash memory is configured for quad in the registers, so it can't understand standard mode.
Is there something I might be missing to configure in the registers or something else I forgot? Thanks in advance.
03-20-2018 01:33 AM
Even if I send erase, read or write commands, everything goes only through one lane (Q0). Any ideas? =/
Thanks in advance.
03-18-2019 10:40 AM
DId you ever resolve this problem? I'm seeing a similar issue when working with the VCU118 eval board. In memory there are also commands to set quad read/write mode, but I haven't been able to configure these properly.