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Visitor hubaokun
Visitor
1,833 Views
Registered: ‎11-08-2017

Axi dma S2MM receive data are not all perfectly normal.

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Hi, anybody

 

     It seems that I succeeded in receiving data in cycling axi dma mode. In the meanwhile, I also met some problems, because the data received are not all perfectly normal.

 

    Here,  I send a series of data from 0 to 2047 according to the s2mm_tdata.

 

xilinx4.PNG

 

XILINX1.PNG

 

then , I found such a problem in the sdk memory debug window.

 

0x01001000 is the first buffer starting address,  the buffer length is 2048,  and 0x01003000 is next description buffer starting address.....

 

xilinx9.PNG

 

 

 

xilinx2.PNG

 

In the above pictures, the s2mm_data lost 5 numbers (4、5、6、7、8)  behind (0、1、2、3),and  after the last number 2047, there are 5 empty spaces...... The same situation is also suitable for the following description buffer.  Why is it?

 

Here is my block desgin.

 

xilinx5.PNG

I don't know why . Who can tell me where the problem is?   Thank you so much.

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Scholar ronnywebers
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2,652 Views
Registered: ‎10-10-2014

Re: Axi dma S2MM receive data are not all perfectly normal.

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@hubaokun, I think it's indeed unavoidable that the DMA controller takes in a few words. It has some pipelining registers at the input (and output). They just caputere the very first incoming data words until the pipeline is filled up (then TREADY goes low). 

 

 

Isn't it only your very first frame that shows strange data? Doesn't it become ok in the 2nd frame?

 

I remember having a similar issue, and I added an 'enable' on my incoming datastream (using a AXI GPIO pin, but you might do it with an AXI Lite reg too), to hold it off until DMA was setup completely and ready to receive data. So my datasource did not set TVALID permanently to '1', only after it was enabled, so I had time to setup my DMA.  Also I added an AXI stream fifo to have better throughput. 

 

I did put an ILA on the AXI stream and AXI control bus, to better understand what was happening. you can then see effectively what happens on the interface (trigger on reset, or DMA enable, ..).

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Visitor hubaokun
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Registered: ‎11-08-2017

Re: Axi dma S2MM receive data are not all perfectly normal.

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xilinx.PNG

 

Maybe that's the cause of the problem. In cyclic mode, perhaps it is still impossible to avoid this case.

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Scholar ronnywebers
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Registered: ‎10-10-2014

Re: Axi dma S2MM receive data are not all perfectly normal.

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any idea why the TLAST line in your simulation window has a red color? That looks like a driving conflict ?

 

The axi stream that goes to your DMA, is it coming from an external source which we don't see in the block diagram?

** kudo if the answer was helpful. Accept as solution if your question is answered **
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Visitor hubaokun
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Registered: ‎11-08-2017

Re: Axi dma S2MM receive data are not all perfectly normal.

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hi, @ronnywebers

    Glad to see your reply, it's a pity, there is an obvious negligence in s2mm_last(red line),  after I fixed this mistake, that's still the case .

    Here , the axi stream comes from fft's index (from 0 to 2047) , in fact, the s2mm_count is also from the same  fft's index ( s2mm_tdata is just half  a cycle slower than s2mm_count by inverting the clock). 

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Scholar ronnywebers
Scholar
2,653 Views
Registered: ‎10-10-2014

Re: Axi dma S2MM receive data are not all perfectly normal.

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@hubaokun, I think it's indeed unavoidable that the DMA controller takes in a few words. It has some pipelining registers at the input (and output). They just caputere the very first incoming data words until the pipeline is filled up (then TREADY goes low). 

 

 

Isn't it only your very first frame that shows strange data? Doesn't it become ok in the 2nd frame?

 

I remember having a similar issue, and I added an 'enable' on my incoming datastream (using a AXI GPIO pin, but you might do it with an AXI Lite reg too), to hold it off until DMA was setup completely and ready to receive data. So my datasource did not set TVALID permanently to '1', only after it was enabled, so I had time to setup my DMA.  Also I added an AXI stream fifo to have better throughput. 

 

I did put an ILA on the AXI stream and AXI control bus, to better understand what was happening. you can then see effectively what happens on the interface (trigger on reset, or DMA enable, ..).

** kudo if the answer was helpful. Accept as solution if your question is answered **
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Visitor hubaokun
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1,755 Views
Registered: ‎11-08-2017

Re: Axi dma S2MM receive data are not all perfectly normal.

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hi, @ronnywebers

 

   Thank you so much for your advice. Yes, not only the first frame shows strange data , the following frames show the same problem. I use the axi dma in SG cyclicing mode.

   I agree with your opinion, so maybe I should add an 'enable' signal  before the dma engine is set up , and the axi stream fifo is also interesting, I'll try it later. Thanks again for your support.

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