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Adventurer
Adventurer
610 Views
Registered: ‎07-30-2018

Re: BRAM Acces to write it from PL and read from PS and compute that data

Sir..as you said i have DONE IT in a modular way.and iam getting expected results.but i have one doubt...how should i use "AXI GPIO" in this...

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Adventurer
Adventurer
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Registered: ‎07-30-2018

Re: BRAM Acces to write it from PL and read from PS and compute that data

sir i have attached The BD...here iam getting this error in implementation...?what can be the problem..please sir help me out!!  THANKS @ronnywebersblock_design.pngBD is like this..that i designederror.pngThis is the error highlighted

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Adventurer
Adventurer
594 Views
Registered: ‎07-30-2018

Re: BRAM Acces to write it from PL and read from PS and compute that data

Sir i have solved the Earlier issues and able to generate bitstream..but iam still..not able to read data from PL....what can be the issue?..i have attached BD and SDK program and in ILA iam getting 32 bit zeros..what can be the issue? ila.png32 bit zeros!why? ..please..let me know..just help this one time more! THANKS @ronnywebersUntitled.pngthis is the BD..is there any corrections required?PS_CODE_SNIPPET.png

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Scholar ronnywebers
Scholar
586 Views
Registered: ‎10-10-2014

Re: BRAM Acces to write it from PL and read from PS and compute that data

hello, that's starting to look good, think you're almost there. I'd start by expanding the ILA with more probes, and attache all the signals of the BRAM to the ILA, so you can see all the writes and reads to / from the RAM

You could also bringout the 'state' of your FSM to the IP, so you can even monitor that on the ILA, it will help you see what's going on.

I see you used the GPIO to 'sink' the dout of the memory, that's of course an option, but you could also have done this in a different way, and read the data from memory by your FSM, I thought that was your plan anyway. Or you could connect the data from the RAM to one of the AXI Lite registers in your custom IP, that's also an option. you'll have to 'consume' that data somewhere, otherwise the optimiser will throw these connections away if. don't be tempted dough to start reading the BRAM throug AXI4 Lite, you better read that directly through the memory map.

Why I mentioned GPIO somewhere in the beginning was that you could 'trigger/enable' your example to start doing something using a GPIO pin. But now that you have a custom AXI Lite IP with the FSM inside, you could as well trigger it through one of the AXI registers. The GPIO is somewhat simpeler to get started with. I'm not sure if you worked with this before? If not, here's a great and simple tutorial from fpgadeveloper.com

That tutorial shows how to send 2 values to your custom IP, and get the multiplied result back. 

Hope this helps you again a step further, you're getting very close. Btw, feel free to kudo some answers, it's the only salary we get as a volunteer on the forum :-)

 

 

** kudo if the answer was helpful. Accept as solution if your question is answered **
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Scholar ronnywebers
Scholar
585 Views
Registered: ‎10-10-2014

Re: BRAM Acces to write it from PL and read from PS and compute that data

maybe one more thing : I see you have a 32-bit address interface to the BRAM. you probably have a smaller memory, so less address lines would be ok too I guess. But probably the optimizer handles that for you.

Also, you write '0x55' to the memory, but if I'm correct it's a 32-bit memory, so you could also write '0x12345678'

but make sure to use the ILA to debug your design!

** kudo if the answer was helpful. Accept as solution if your question is answered **
Adventurer
Adventurer
567 Views
Registered: ‎07-30-2018

Re: BRAM Acces to write it from PL and read from PS and compute that data

Sir,i have a massive doubt..just see this FSM BLOCK code which i have designed i used it with BASIC RAM module ...and see the simulaton too....HERE in the FSM should DIN and ADDR be the outputs to BRAM controller,

or have i designed correctly..."Simulation" along with FSM_verilog module

//FSM CONTROLLER//

module FSM_AND_BRAM(
input wire CLK,
input wire [31:0]DIN,
input wire [31:0]ADDR,
input wire RST,
input wire [3:0]WE,
input wire EN,
output wire[2:0] CURRENT_STATE,
output wire [31:0]DOUT
);
///////////////////////////////////////////////////////////////////////////////////
reg [31:0]DOUT_SIG      = 32'h00000000;
reg [2:0]STATE_SIG      = 3'b000;
reg [31:0]MEM[1023:0];
reg [31:0]DIN_SIG       = 32'h00000000;
reg [31:0]ADDR_SIG      = 32'h00000004;
///////////////////////////////////////////////////////////////////////////////////
parameter INIT          = 3'b000;
parameter READ_DATA     = 3'b001;
parameter INC_ADDR_DATA = 3'b010;
parameter WRITE_BACK    = 3'b011;
///////////////////////////////////////////////////////////////////////////////////
assign DOUT             = DOUT_SIG;
assign DIN              = DIN_SIG;
assign CURRENT_STATE    = STATE_SIG; 
assign ADDR             = ADDR_SIG;
//////////////////////////////////////////////////////////////////////////////////
always@(posedge CLK)
begin

case(STATE_SIG)

INIT:
begin
 if(RST)
   begin
    STATE_SIG           <= INIT;
    DOUT_SIG            <= 32'h00000000;
    DIN_SIG             <= 32'h00000000;
    ADDR_SIG            <= 32'h00000004;
    end  
  else
  
   STATE_SIG            <= READ_DATA;
end

READ_DATA:
 begin
  DOUT_SIG              <= MEM[ADDR_SIG]; //Read the data at each and every Address.
  STATE_SIG             <= INC_ADDR_DATA;
end

INC_ADDR_DATA:
 begin
  DIN_SIG               <= DIN_SIG  + 32'h04040404; //Increment Data
  ADDR_SIG              <= ADDR_SIG + 32'h00000004;//Increment address
  STATE_SIG             <= WRITE_BACK;
 end

WRITE_BACK:
 begin
  if(EN)
   begin
    if(WE == 4'b0001)
     begin
      MEM[ADDR_SIG]    <= DIN_SIG; //Write Back mode and the goes back to READ_DATA state
      STATE_SIG        <= READ_DATA;
      end
    end   
 end 

default:
  begin
   DOUT_SIG            <= 32'h00000000;
   DIN_SIG             <= 32'h00000000;
   ADDR_SIG            <= 32'h00000004;
  end
 endcase
end
endmodule

simu_CORRECT.pngI got this simulation..with FSM and the BRAM You provided!!let me know sir 

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Adventurer
Adventurer
549 Views
Registered: ‎07-30-2018

Re: BRAM Acces to write it from PL and read from PS and compute that data

sir waiting for your reply...:)

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Scholar ronnywebers
Scholar
534 Views
Registered: ‎10-10-2014

Re: BRAM Acces to write it from PL and read from PS and compute that data

this thread is starting to look like an interactive tutorial :-) ...

you still did not decouple the memory from the FSM, the memory is 'inside' your FSM  ... memory should go into 1 file, FSM in the other. That will later allow you to more easily migrate your FSM to a packaged IP, and interface with the block memory that you originally showed in your block diagram.

so remove this from your FSM :

reg [31:0]MEM[1023:0];

and create a separate memory (single or dual port, see UG901 as I explained in a previous reply)

So I mean this :

BRAM.jpg

so top side is the block diagram you were targetting in Vivado

bottom is the testbench that I think you should try to build, so you can more easily package your FSM as a custom IP and incorporate it in Vivado.

I've put the 2 options in that testbench : controlling the FSM with GPIO, or through AXI4 Lite registers. The GPIO way is probably easier to get started with, AXI4 Lite requires some 'BFM' (Bus Functional Model) to simulate the Zynq writing to and reading from the AXI4 lite registers. Not sure what you know about this, if that knowledge is currently zero, I'd first try and get your FSM working using simple GPIO lines that start, stop, reset, ... your FSM. If that works fine, try to add the AXI4 Lite interface. I gave you the example from fpgadeveloper.com for this to get you started. But that will not explain how to use a BFM ... so again, get started with GPIO for now looks easier to me. So the blocks in 'yellow' are for later, after you went through the fpgadeveloper.com tutorial. After that, you could go through this tutorial , it shows you how to use a simple BFM to simulate AXI transactions. Xilnx also has an AXI BFM IP, but that uses SystemVerilog to control it, I cannot help you with that. I just used the BFM from the tutorial I just gave your.

Also to simulate the memory, you can choose between a single port RAM that you initialize or not with constant values (so you'd only use a port between your FSM and the memory). Or use a dual port RAM that you initialize from the stimuli of your testbench, that's up to you. First option looks easier to me.

you could even instantiate a block memory controller + generator, but again that's more complicated. Just take UG901 and create a single port memory.

** kudo if the answer was helpful. Accept as solution if your question is answered **
Adventurer
Adventurer
528 Views
Registered: ‎07-30-2018

Re: BRAM Acces to write it from PL and read from PS and compute that data

Sir..this thread ..is basically my new lease of life in FPGA...so thank you for that :)

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Adventurer
Adventurer
506 Views
Registered: ‎07-30-2018

Re: BRAM Acces to write it from PL and read from PS and compute that data

Good afternoon sir,Illustrate this with an Example,this point quoted by yourself"'id first try and get your FSM working using simple GPIO lines that start, stop, reset, ... your FSM...."  I dont have an idea how to verify with axi gpio,with start,stop,reset,can you illustrate an example..and i will send the code ..which i have written and simulation..i have removed the memory... from the fsm....my questions are how do i verify..fsm with gpio...as in testbench terms..iam

module FSM_D(
input wire CLK,
input wire RST,
input wire [1:0]START_STATE,
input wire [1:0]STOP_STATE,
input wire [1:0]RESET_STATE,
output wire [31:0]ADDR,
output wire [31:0]DIN
);
///////////////////////////////////////////////////////////////////////////////////
reg [1:0]CURRENT_STATE  = 2'b00;
reg [31:0]DIN_SIG       = 32'h00000000;
reg [31:0]ADDR_SIG      = 32'h40000000;
///////////////////////////////////////////////////////////////////////////////////
parameter START         = 2'b00;
parameter STOP          = 2'b01;
parameter RESET         = 2'b10;
///////////////////////////////////////////////////////////////////////////////////
assign DIN              = DIN_SIG;
assign START_STATE      = START;
assign STOP_STATE       = STOP;
assign RESET_STATE      = RESET;
assign ADDR             = ADDR_SIG;
//////////////////////////////////////////////////////////////////////////////////
always@(posedge CLK)
begin

case(CURRENT_STATE)

START:
begin
 if(RST == 0)
   begin
     DIN_SIG           <= DIN_SIG  + 32'h04040404; //Increment Data
     ADDR_SIG          <= ADDR_SIG + 32'h00000004;//Increment address
     CURRENT_STATE     <= START;
   end  
else
  
   CURRENT_STATE       <= STOP;
end

STOP:
 begin
// DIN_SIG               <= 32'h00000000;
// ADDR_SIG              <= 32'h40000000;  
 CURRENT_STATE         <= RESET;
 end
RESET:
 begin
   DIN_SIG             <= 32'h00000000;
  ADDR_SIG             <= 32'h40000000;  
  CURRENT_STATE        <= START;
 end




default:
  begin
   DIN_SIG            <= 32'h00000000;
   ADDR_SIG           <= 32'h40000000;
  end
 endcase
end
endmodule

simulation.pngthis is the simulation of FSM iam checking just the fsm ..not with bram..since in bram ...the bram output ie;DOUT is xxxxx...i need to know..what to do in simulation regardconfused seeing the link ..you have given...please..just see if my code and simulation are correct..and how to check this fsm with GPIO,with start,stop,reset...please..need some clarity on that..

                                                                                                                                          THANKS IN ADVANCE

                                                                                                                                              @ronnywebers 

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Adventurer
Adventurer
503 Views
Registered: ‎07-30-2018

Re: BRAM Acces to write it from PL and read from PS and compute that data

after some changes in teraterm..iam reading negative values..tera_values_read.png

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Adventurer
Adventurer
491 Views
Registered: ‎07-30-2018

Re: BRAM Acces to write it from PL and read from PS and compute that data

i have changed put control on code in gpio..go,done and reset signal..and simulation too..to control..the fsm..but when iam trying to simulate this with bram ..it shows dout as xxxx...as it has no effect on the BRAM..WHAT Can be the reason..help me out patiently sir THANKS @ronnywebers tb_simu.pnggo signal to start and done for stop

module FSM_D(
input wire CLK,
input wire RST,
input wire READY,
input wire GO,
output wire DONE,
output wire [31:0]ADDR,
output wire [31:0]DIN
);
///////////////////////////////////////////////////////////////////////////////////
reg [2:0]CURRENT_STATE  = 3'b000;
reg [31:0]DIN_SIG       = 32'h00000000;
reg [31:0]ADDR_SIG      = 32'h40000000;
reg DONE_SIG            = 1'b0;
reg VALID               = 1'b0;
reg ADDR_EN             = 1'b0;
///////////////////////////////////////////////////////////////////////////////////
parameter RESET_STATE   = 3'b000;
parameter IDLE_STATE    = 3'b001;
parameter START         = 3'b010;
parameter STOP          = 3'b011;
///////////////////////////////////////////////////////////////////////////////////
assign DONE             = DONE_SIG;
assign DIN              = DIN_SIG;
assign ADDR             = ADDR_SIG;
//////////////////////////////////////////////////////////////////////////////////
always@(posedge CLK)
begin

case(CURRENT_STATE)

RESET_STATE:
begin
 if(RST)
   begin
      DIN_SIG          <= 32'h00000000;
      ADDR_SIG         <= 32'h40000000;
      CURRENT_STATE    <= RESET_STATE;   
   end  
else
  
   CURRENT_STATE       <= IDLE_STATE;
end

IDLE_STATE:
 begin
  begin
   DONE_SIG            <= 1'b0;
   ADDR_EN             <= 1'b0;
   VALID               <= 1'b0;
   DIN_SIG             <= 32'h00000000;
   ADDR_SIG            <= 32'h40000000; 
 CURRENT_STATE         <= IDLE_STATE;
  end
 if(GO == 1)
   CURRENT_STATE       <= START;  
 end
 
START:
 begin
  begin
   DIN_SIG             <= DIN_SIG  + 32'h04040404; //Increment Data
   ADDR_SIG            <= ADDR_SIG + 32'h00000004;//Increment address
   ADDR_EN             <= 1'b1;
   VALID               <= 1'b1;
   CURRENT_STATE       <= STOP;
   end
   if(READY == 1'b1)
   CURRENT_STATE       <= START;

 end


STOP:
 begin
  begin
   CURRENT_STATE       <= STOP;
   DONE_SIG            <= 1'b1;
  end
    if(GO == 0)
     CURRENT_STATE     <= IDLE_STATE;
//     DONE_SIG          <= 1'b1;
  end


default:
  begin
   DIN_SIG            <= 32'h00000000;
   ADDR_SIG           <= 32'h40000000;
   CURRENT_STATE      <= RESET_STATE;
  end
 endcase
end
endmodule
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Scholar ronnywebers
Scholar
482 Views
Registered: ‎10-10-2014

Re: BRAM Acces to write it from PL and read from PS and compute that data

great that you got your head around the 'gpio' thing :-) Once you get it, it's quiet simpel :-)

about the negative values, I think you are not formatting the values correctly as hex, have a look at this post

something like this will probably give you a more understandable result for a 32-bit hex value :

printf("0x%08x",your_variable);

the negative values come from the most significant bit being '1' (see diff between signed/unsigned ints)

I cannot tell you exactly why your RAM is behaving strange, can you share the testbench (attach it to the post) and the memory source file, I need to see how it is hooked up. Your FSM seems to do generate corrrect signals, address increments etc). 

Now you should focus on the signals between your FSM and the (simulated) memory : visualise the addresss, din, dout, write enable, read ... signals, anything you have in between.

At this point you could also try to go back to your device, and use an ILA to debug thing further : connect all the signals between your FSM and BRAM, so you can see what's happening.

** kudo if the answer was helpful. Accept as solution if your question is answered **
Adventurer
Adventurer
470 Views
Registered: ‎07-30-2018

Re: BRAM Acces to write it from PL and read from PS and compute that data

1.) The GPIO method was implemented ...my data in PL was not being Read.(ie;READ_DATA = 0)

2.) I did the change you suggested..and iam getting values..of 32 bit..teratem values attached..(Series of values)

3.)Here the main issue is DIN and ADDR..from the FSM are working fine...but in the DOUT of the ram ...iam getting unknown(xxxxxxxx)....i donT get that point..i need help..on that...

4.) There is no effect of the FSM on the BRAM output(DOUT)..I Have attached FSM and BRAM ..along with TESTBENCH...please have a look...

5.) Also DIN AND ADDR Signals from the FSM ..are continuous.(SIMULATION SENT TOO.)

///FSM//


module finite_machine_state(
input wire CLK,
input wire RST,
output wire [31:0]ADDR_OUT,
//output wire[1:0]STATE,
output wire [31:0]DIN_OUT
);
///////////////////////////////////////////////////////////////////////////////////
reg [1:0]CURRENT_STATE  = 2'b00;
reg [31:0]DIN_SIG       = 32'h00000000;
reg [31:0]ADDR_SIG      = 32'h40000000;
///////////////////////////////////////////////////////////////////////////////////
parameter RESET         = 2'b00;
parameter START         = 2'b01;
parameter DONE          = 2'b10;
///////////////////////////////////////////////////////////////////////////////////
//assign DIN_IN           = DIN_SIG;
//assign ADDR_IN          = ADDR_SIG;
assign DIN_OUT          = DIN_SIG;
assign ADDR_OUT         = ADDR_SIG;
//////////////////////////////////////////////////////////////////////////////////
always@(posedge CLK)
begin

case(CURRENT_STATE)

RESET:
begin
 if(RST)
   begin
     CURRENT_STATE     <= RESET;
     DIN_SIG           <= 32'h00000000;
     ADDR_SIG          <= 32'h40000000;
   end  
else
  
   CURRENT_STATE       <= START;
end

START:
 begin
 DIN_SIG               <= 32'h00000000;
 ADDR_SIG              <= 32'h40000000;  
 CURRENT_STATE         <= DONE;
 end
DONE:
 begin
  DIN_SIG              <= DIN_SIG  + 32'h04040404; //Increment Data
  ADDR_SIG             <= ADDR_SIG + 32'h00000004;//Increment address
  CURRENT_STATE        <= DONE;
 end




default:
  begin
   DIN_SIG            <= 32'h00000000;
   ADDR_SIG           <= 32'h40000000;
  end
 endcase
end
endmodule




//BRAM//

module ram_mem
(input wire CLK,
input wire EN,
input wire WE,
input wire RST,
input wire [31:0]ADDR,
input wire [31:0]DIN,
output wire [31:0]DOUT);
//////////////////////////////////////////////////////////////////////////////////////
reg [31:0] ram [1023:0];
reg [31:0] DOUT_SIG = 32'h00000000;
//////////////////////////////////////////////////////////////////////////////////////
assign DOUT     = DOUT_SIG;

////////////////////////////////////////////////////////////////////////////////////// 
always @(posedge CLK)
begin

begin
 if (EN) //optional enable
 begin
 if (WE) //write enable
 ram[ADDR] <= DIN;
 if (RST) //optional reset
 DOUT_SIG <= 0;
 else
 DOUT_SIG <= ram[ADDR];
 end
end
end

//finite_machine_state f1 (.CLK(CLK),.RST(RST),.ADDR_OUT(ADDR),.DIN_OUT(DIN));

endmodule




//TESTBENCH//

module tb_fsm_ram();
reg CLK;
reg RST;
reg EN;
reg WE;
reg[31:0]ADDR;
reg [31:0]DIN;
wire [31:0]DOUT;
wire [31:0]ADDR_OUT;
wire [31:0]DIN_OUT;


ram_mem r1(.CLK(CLK),.RST(RST),.EN(EN),.WE(WE),.DIN(DIN),.ADDR(ADDR),.DOUT(DOUT));
finite_machine_state f1 (.CLK(CLK),.RST(RST),.ADDR_OUT(ADDR_OUT),.DIN_OUT(DIN_OUT));

initial
begin
CLK    = 1'b0;
end
always
#5 CLK = ~CLK;

initial
 begin
  RST  = 1'b1;
 #10;
  RST  = 1'b0;
 end

initial
 begin
  EN  = 1'b0;
 #20;
  EN  = 1'b1;
 end


initial
begin
 DIN  = 32'h0a3d70a3;
 ADDR = 32'd0;
 WE   = 1'b1;
#100;

DIN   = 32'h0e560418;
ADDR  = 32'd1;
WE    = 1'b1;
#100;

DIN   = 32'h147ae147;
ADDR  = 32'd2;
WE    = 1'b1;
#100;


DIN   = 32'h20c49ba5;
ADDR  = 32'd3;
WE    = 1'b1;
#100;

ADDR  = 32'd0;
WE    = 32'b0;
#100;

ADDR  = 32'd1;
WE    = 32'b0;
#100;

ADDR  = 32'd2;
WE    = 32'b0;
#100;

ADDR  = 32'd3;
WE    = 32'b0;
#100;




end

endmodule



reading_data_change.pngi think continuous din and Addr values ..are impacting on this..ILA_NEW.pngILA ..what i suggested continous values of din and addr...But no impact On DOUT of BRAM..si.pngsimulation of FSM with BRAM...i have sent you FSM CODE please tell me how to START,STOP,RESET...in this RTL CODE...

5.) In ILA also it is stuck in state 2 -> ie; START..state..please tell me what corrections ..i have to do in my FSM code.and later testbench..and how to get DOUT from RAM through my FSM which acts as controller..

                                                                                                                                                                                 THANKS @ronnywebers 

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Adventurer
Adventurer
465 Views
Registered: ‎07-30-2018

Re: BRAM Acces to write it from PL and read from PS and compute that data

I think my FSM CODE and DOUT of BRAM is the main issue...it is showing Unknown...just tell what to change in FSM and testbench...waveform attached for better underderstanding....

//FSM//

module finite_machine_state(
input wire CLK,
input wire RST,
output wire [31:0]ADDR,
//output wire[1:0]STATE,
output wire [31:0]DIN

);
///////////////////////////////////////////////////////////////////////////////////
reg [1:0]CURRENT_STATE  = 2'b00;
reg [31:0]DIN_SIG       = 32'h00000000;
reg [31:0]ADDR_SIG      = 32'h40000000;
///////////////////////////////////////////////////////////////////////////////////
parameter RESET         = 2'b00;
parameter START         = 2'b01;
parameter DONE          = 2'b10;
///////////////////////////////////////////////////////////////////////////////////

assign DIN              = DIN_SIG;
assign ADDR             = ADDR_SIG;
//////////////////////////////////////////////////////////////////////////////////
always@(posedge CLK)
begin

case(CURRENT_STATE)

RESET:
begin
 if(RST)
   begin
     CURRENT_STATE     <= RESET;
     DIN_SIG           <= 32'h00000000;
     ADDR_SIG          <= 32'h40000000;
   end  
else
  
   CURRENT_STATE       <= START;
end

START:
 begin
 DIN_SIG               <= 32'h00000000;
 ADDR_SIG              <= 32'h40000000;  
 CURRENT_STATE         <= DONE;
 end
DONE:
 begin
  DIN_SIG              <= DIN_SIG  + 32'h04040404; //Increment Data
  ADDR_SIG             <= ADDR_SIG + 32'h00000004;//Increment address
  CURRENT_STATE        <= DONE;
 end




default:
  begin
   DIN_SIG            <= 32'h00000000;
   ADDR_SIG           <= 32'h40000000;
  end
 endcase
end
endmodule




//TESTBENCH//


module tb_fsm_ram();
reg CLK;
reg RST;
reg EN;
reg WE;
reg[31:0]ADDR;
reg [31:0]DIN;
wire [31:0]DOUT;



ram_mem r1(.CLK(CLK),.RST(RST),.EN(EN),.WE(WE),.DIN(DIN),.ADDR(ADDR),.DOUT(DOUT));


initial
begin
CLK    = 1'b0;
end
always
#5 CLK = ~CLK;

initial
 begin
  RST  = 1'b1;
 #10;
  RST  = 1'b0;
 end

initial
 begin
  EN  = 1'b0;
 #20;
  EN  = 1'b1;
 end


initial
begin
 DIN  = 32'h0a3d70a3;
 ADDR = 32'd0;
 WE   = 1'b1;
#100;

DIN   = 32'h0e560418;
ADDR  = 32'd1;
WE    = 1'b1;
#100;

DIN   = 32'h147ae147;
ADDR  = 32'd2;
WE    = 1'b1;
#100;


DIN   = 32'h20c49ba5;
ADDR  = 32'd3;
WE    = 1'b1;
#100;

ADDR  = 32'd0;
WE    = 32'b0;
#100;

ADDR  = 32'd1;
WE    = 32'b0;
#100;

ADDR  = 32'd2;
WE    = 32'b0;
#100;

ADDR  = 32'd3;
WE    = 32'b0;
#100;




end

endmodule

simulations_check.pngTHIS IS the case!

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Adventurer
Adventurer
456 Views
Registered: ‎07-30-2018

Re: BRAM Acces to write it from PL and read from PS and compute that data

i understood ..now ..the gpio way .It was one in which you control your FSM through FPGA Switches for inputs and LED for the output....its easier actually..sorry got it really late! THANKS @ronnywebers  

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Scholar ronnywebers
Scholar
449 Views
Registered: ‎10-10-2014

Re: BRAM Acces to write it from PL and read from PS and compute that data

let's first focus on your FSM and simulation ... btw, always check all the logs of your simulator, maybe there are some clues there. Red means that the output is undefined, the simulator cannot unambiguously determine the value of DOUT. 

first of all, make sure to understand that everything in your testbench, fsm, ... happens on the rising edge of the clock. So if you set 'EN' high, the 'EN' is only read at the NEXT rising edge. Same goes for any other signal, like WE, RST and so on.

You can see this happen, because the red 'XXX' appear right at the first rising edge where you set 'EN' high. 

again, I don't know Verilog or how it's interpreted by Vivado, but if I look at your code of the RAM, I can see you used 'rams_sp_rf_rst.v' form UG901, which is a good idea to get started with. that code says :

always @(posedge clk)
begin
  if (en) //optional enable
  begin
    if (we) //write enable
      ram[addr] <= di;
    if (rst) //optional reset
      dout <= 0;
    else
      dout <= ram[addr];
end
end

so if you look at the nesting of the 'if's, I think the RST is ignored when EN is low... can you try to set EN high, then wait a few clock cycles, then toggle the RST high, wait a few clock cycles, then make 'RST' back '0'. See if the red 'XXX' change to green. 

 

 

by the way :

your memory is 32-bit wide, and has 1024 entries. to address each 32-bit word, you need 1024 addresses, generated with 2^10 -> 10 address lines. So the 32-bit address lines are rather overkill or ignored anyway, your 1024-entry RAM can only use the lowest 10 address lines (it ignores the rest, and will 'wrap around') 

input wire [31:0]ADDR,
input wire [31:0]DIN,
output wire [31:0]DOUT);
//////////////////////////////////////////////////////////////////////////////////////
reg [31:0] ram [1023:0];

but that is probably not the issue ... but I'm sure Vivado simulator will tell you this in some log file (some warning like 'address size mismatch')

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Re: BRAM Acces to write it from PL and read from PS and compute that data

1.)As you said i instantiated both the FSM and Single PORT RAM in a testbench..and i got the following simulation..(ATTACHED).

2.)AS you said ..initially i kept enable at 1 and then after some clock cycles ..toggled the reset =0 and then back at reset= 1,and then again at reset = 0...but whats happeneing is the xxx on the DOUT of the BRAM has been removed...but ..the DATA_IN and ADDRESS generated from the FSM..has no effect on the DOUT of the bram.

ie;whatever values iam passing through DIN and ADDRESS in the testbench..that is the ones which are being seen.on the DOUT OF THE BRAM...not the FSM generated DATA_IN and ADDRESS.

3.)I have attached the simulation.and testbench..tell me what corrections i need to do.

4.) My point is that my FSM has no effect on the BRAM..iam getting the same values...

my question is..should my values from the FSM(ie;DATA_IN & ADDRESS) Alter values of my dout..?"MAJOR QUESTION THIS ONE IS.. "

ie;should the values of DATA_IN and ADDRESS_IN from FSM Alter values of DATA_IN and ADDRESS given from testbench(ie;DATA_IN & ADDRESS from BRAM

ss.pngThis is the simulation.... Din and address from Testbench..is the output ..we are saying on bram..confused on that?

//Testbench//


module tb_fsm_ram();
reg CLK;
reg RST;
reg GO;
reg REST_SIG;
reg EN;
reg WE;
reg [31:0]ADDR;
reg [31:0]DIN;
wire [31:0]ADDR_FSM;
wire [31:0]DATA_FSM;
wire DONE;
wire [31:0]DOUT;



ram_mem r1(.CLK(CLK),.RST(RST),.EN(EN),.WE(WE),.GO(GO),.REST_SIG(REST_SIG),.ADDR_IN(ADDR),.DIN_IN(DIN),.DONE(DONE),.DOUT(DOUT));
finite_machine_state f1 (.CLK(CLK),.RST(RST),.GO(GO),.REST_SIG(REST_SIG),.DIN_OUT(DATA_FSM),.ADDR_OUT(ADDR_FSM),.DONE(DONE));


initial
begin
CLK    = 1'b0;
end
always
#5 CLK = ~CLK;

initial
 begin
  RST  = 1'b1;
 #10;
  RST  = 1'b0;
 end

//initial
// begin
//  EN  = 1'b0;
// #20;
//  EN  = 1'b1;
// end



initial
begin
CLK    = 1'b0;
end
always
#5 CLK = ~CLK;

initial
 begin
  EN  = 1'b0;
 #10;
  EN  = 1'b1;
 end


initial
 begin
  RST  = 1'b0;
 #30;
  RST  = 1'b1;
  #70
  RST  = 1'b0;
  #30;
    RST  = 1'b1;
    #40
     RST  = 1'b0; 
 end

//initial
// begin
//  EN  = 1'b0;
// #10;
//  EN  = 1'b1;
// end


initial
begin
DIN  = 32'h00000000;
 ADDR = 32'd0;
 WE   = 1'b1;
 GO  = 0;
REST_SIG = 0;
#200;

DIN  = 32'h0a3d70a3;
 ADDR = 32'd1;
 WE   = 1'b1;
 GO  = 1;
REST_SIG = 1;
#100;

DIN   = 32'h147ae147;
ADDR  = 32'd2;
WE    = 1'b1;
GO    = 1;
REST_SIG = 1;
#100;



DIN   = 32'h20c49ba5;
ADDR  = 32'd3;
WE    = 1'b1;
GO    = 1;
REST_SIG = 1;
#100;
//DIN   = 32'h00000000;
ADDR  = 32'd0;
WE    = 1'b0;
GO  = 0;
REST_SIG = 0;
#100;

ADDR  = 32'd1;
WE    = 1'b0;
GO  = 0;
REST_SIG = 0;
#200;

ADDR  = 32'd2;
WE    = 1'b0;
GO  = 0;
REST_SIG = 0;
#100;

ADDR  = 32'd3;
WE    = 1'b0;
GO  = 0;
REST_SIG = 0;
#100;


end
endmodule
module tb_fsm_ram();
reg CLK;
reg RST;
reg GO;
reg REST_SIG;
reg EN;
reg WE;
reg [31:0]ADDR;
reg [31:0]DIN;
wire [31:0]ADDR_FSM;
wire [31:0]DATA_FSM;
wire DONE;
wire [31:0]DOUT;



ram_mem r1(.CLK(CLK),.RST(RST),.EN(EN),.WE(WE),.GO(GO),.REST_SIG(REST_SIG),.ADDR_IN(ADDR),.DIN_IN(DIN),.DONE(DONE),.DOUT(DOUT));
finite_machine_state f1 (.CLK(CLK),.RST(RST),.GO(GO),.REST_SIG(REST_SIG),.DIN_OUT(DATA_FSM),.ADDR_OUT(ADDR_FSM),.DONE(DONE));


initial
begin
CLK    = 1'b0;
end
always
#5 CLK = ~CLK;

initial
 begin
  RST  = 1'b1;
 #10;
  RST  = 1'b0;
 end

//initial
// begin
//  EN  = 1'b0;
// #20;
//  EN  = 1'b1;
// end



initial
begin
CLK    = 1'b0;
end
always
#5 CLK = ~CLK;

initial
 begin
  EN  = 1'b0;
 #10;
  EN  = 1'b1;
 end


initial
 begin
  RST  = 1'b0;
 #30;
  RST  = 1'b1;
  #70
  RST  = 1'b0;
  #30;
    RST  = 1'b1;
    #40
     RST  = 1'b0; 
 end

//initial
// begin
//  EN  = 1'b0;
// #10;
//  EN  = 1'b1;
// end


initial
begin
DIN  = 32'h00000000;
 ADDR = 32'd0;
 WE   = 1'b1;
 GO  = 0;
REST_SIG = 0;
#200;

DIN  = 32'h0a3d70a3;
 ADDR = 32'd1;
 WE   = 1'b1;
 GO  = 1;
REST_SIG = 1;
#100;

DIN   = 32'h147ae147;
ADDR  = 32'd2;
WE    = 1'b1;
GO    = 1;
REST_SIG = 1;
#100;



DIN   = 32'h20c49ba5;
ADDR  = 32'd3;
WE    = 1'b1;
GO    = 1;
REST_SIG = 1;
#100;
//DIN   = 32'h00000000;
ADDR  = 32'd0;
WE    = 1'b0;
GO  = 0;
REST_SIG = 0;
#100;

ADDR  = 32'd1;
WE    = 1'b0;
GO  = 0;
REST_SIG = 0;
#200;

ADDR  = 32'd2;
WE    = 1'b0;
GO  = 0;
REST_SIG = 0;
#100;

ADDR  = 32'd3;
WE    = 1'b0;
GO  = 0;
REST_SIG = 0;
#100;


end
endmodule

)..during simulation of BRAM..let me know on that!!  

5.)Last point Should i insantantiate ..FSM as child module and make BRAM as the parent module to that...thats the point  where...DOUT OF THE BRAM..shows X(ie.Unknown)...let me know on that..

                                                                                                                                              THANKS @ronnywebers   

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Re: BRAM Acces to write it from PL and read from PS and compute that data

1) I think you have a coding issue in your FSM, I still don't know verilog, but if I look at UG901, chapter 3 -> FSM components -> FSM Example (Verilog), I see you don't follow that template. So I would study that template first, and adapt your FSM accordingly. Look carefully to the 'case' statements, 

so FIRST correct this

2) look again at this block diagram of your testbench that I proposed :

TB.jpg

so your FSM gets 3 control inputs, generated by your testbench : start, done, reset (reset sets your address and data value back to their initial values for example)

your FSM and memory both get the system wide 'clk' and 'rst' signal, which is also generated by the TB

the signals between your FSM and memory are defined by the 'interface' of your memory :

3) look at the 'interface' of your memory :

input clk;
input en;
input we;
input rst;
input [9:0] addr;
input [15:0] di;
output [15:0] dout;

the 'input' signals of the memory need to be generated/controlled by either your FSM or the TB, but NEVER not both. 

* I would generate the clk and rst from your testbench, as these are generally 'system wide signals', used by both the memory and FSM. Generation of your clk and rst looks ok in your testbench

* all other 'input signals' of the memory should be generated (controlled) by your FSM (not by your testbench!)  : en, we, addr, di -> so in each state of your FSM you should make sure that these 4 signals have a corrrect value. Also in the 'reset' state you should give these signals some 'idle' value, so that your memory is not 'written'. So your FSM starts with an initial address and initial value, and then calculates the next address and datavalues 'by itself', it is NOT your TB that should generate the addresses or values, it is your FSM. So that is fundamentally wrong in you concept/head. Your initial goal (if I remember correctly) was to make an FSM that reads values from the memory, does some calculation, and writes back the result. So your FSM should generate the address, data and control signals ...

* the 'dout' is something you could just 'observe' to see what value is stored in the address you provide on the 'di' of your memory. To do this 'verification' of the memory content you can do several things:

a) just observe the array ram[1023:0][31:0] in the simulator, it's contents should get updated when you write. 

b) after your FSM has written it's values, you can create additional states to read back the value. Then observe in the simulator if the values on dout are correct. This is the easiest method

c) later on, you can make your memory 'dual ported' (add PORT A), and check the values int he RAM through PORT A from the testbench - but leave this method for later

Again I think you would win a lot of time by searching a Verilog tutorial (any) of an FSM and a testbench, to get you a head start. You're missing some basic knowledge, and by trial and error you are wasting a lot of time. I would really get a book, read that for a few (like 3) days, and then come back to what you're doing here.

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Re: BRAM Acces to write it from PL and read from PS and compute that data

Sir ..apart ..from that book from pong chu..suggest ..me a good digiatl logic + verillog...

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Re: BRAM Acces to write it from PL and read from PS and compute that data

THANK for your help @ronnywebers 

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Re: BRAM Acces to write it from PL and read from PS and compute that data

1.)As you said...trial and error method..is no use..but i generated all signals WE,EN,DATA_IN,ADDRESS through the FSM...and that part is now fine.

2)Now the final issue is..iam still getting unknown xxxxxx at DOUT of the BRAM....As you said Before ..to keep EN at EN= 1...and after a few clock cycles Toggle the RESET = 1 and After a few Clock Cycles toggle it Back to RESET = 0.....because of that toggle at RESET= 1..it comes back to initial value of DOUT ie;32'h00000000...whenver RESET goes back to 0...xxxx ie; unknown again...need to get of this predicament...just tell me what i need to do...iam close i feel!

THANKS in ADVANCEDOUT_UNKNOWN.png @ronnywebers 

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Re: BRAM Acces to write it from PL and read from PS and compute that data

iam getting DOUT of the BRAM now!dout_coming.pngis this how it should be!!?

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Re: BRAM Acces to write it from PL and read from PS and compute that data

looking better and better ! At some point you can see the value 50505050 being written into the RAM, and 1 cycle later it comes out on DOUT. 

Can you add the ram contents : reg [15:0] ram [1023:0] to your waveform, so you can see what's inside the ram? Also try to post a 'less zoomed out' view, i.e. try to write just 2 values to 2 addresses, then read back these 2 values from the 2 addresses, then you can more easily see everything on your waveforms. If you can write 2 values and verify them, it will also work for 1024 values...

I also saw some strange thing on your initial reset : you generate like 4 pulses, not that this should be a problem, but it would be cleaner to generate a single nice reset pulse:

reset.jpg

so I would make the RESET : '0' between 0 and 100ns, then you make it '1' for 200ns, then you make it '0' for the rest of the time. Depending on the type of simulation, your reset needs to be mimimum 100ns wide. This is probably not needed for the functional simulation that you run, but it's good practice to make a clean reset in a testbench that simulates a real-world power-on reset.

Then make sure you wait at least one after the reset goes low before you enable the 'go' signal

For some reason that is currently unclear to me,  the DOUT signal goes red. I think it is because your memory array starts unitialized. To know the difference between red/orange/green lines in simulation, see this post

So just experiment a bit further, your FSM looks good I think, just curious to see a bit more detail. If you have everything working and close this thread, it would be nice to other users if you share your final code and testbench :-)

 

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Re: BRAM Acces to write it from PL and read from PS and compute that data

1.) Contents in the reg mem[31:0] [1023:0] show...xxxxxx....

2)But i have fixed the part where ..when i was applying RESET_SIGNAL...DOUT = x, but now it shows DOUT = 32'D0;so thats better now.

3.)did the change in RESET ..which you asked.

4.)Intially iam getting some x at dout is that ok?..i will post it,ie;CODE of fsm and testbench..after Testing.sim_ul.pngtwo_data_two_address.pngas you said i wrote two data on two address....and read those two values on output of BRAM..THANKS @ronnywebers 

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Re: BRAM Acces to write it from PL and read from PS and compute that data

Hi,how should i connect my AXI_LITEIP to AXI gpio..ie;how to control GO,RESET_SIGNAL AND DONE...through AXI GPIO!

bLOCK DIAGRAM ATTACHED..just tell me where to connect..these lines!..i have shared attachement of each and every connection for GO,DONE and RESET_SIGNAL...please let me know what i should do!

1.)first attachment is for "GO" signal

2.)second attachemnt is for "RESET_SIGNAL"

3.)Third attachment is for "DONE" signalGO_SIG_BD.png"GO"SIGNALRESET_SIGNAL_BD.png"RESET_SIGNAL"DONE_BD_SIG.png"DONE"signal

THANKS @ronnywebers 

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Re: BRAM Acces to write it from PL and read from PS and compute that data

i HAVE A question....is DONE SIGNAL an input or kind of acknowledgement..output signal..let me know..as i cant figure out how to use AXI GPIO! THANKS @ronnywebers 

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Re: BRAM Acces to write it from PL and read from PS and compute that data

@sam007 

reset : input to your FSM -> AXI GPIO sets this line to '1' so your FSM can jump back to its initial state, reset address counters, and so on.

go : input to your FSM -> GPIO sets this line to '1' to start your FSM

-> you can connect reset and go to the same AXI GPIO (it has 32-pins on each port available), but for now you can use 3 instances of AXI GPIO to keep it simple. 

done : output of your FSM -> read this through an AXI GPIO pin, to know when your FSM has finished. you should 'poll' this line from your software, after you set 'go' to '1'

I think you can do bi-directional IO with an AXI GPIO IP, but for now keep it simple and use the 3'rd AXI GPIO as input to poll the done signal.

side note : I still don't see where the red lines in your RAM content come from, keep searching on that too, I'm sure your RAM should show the contents in the simulator window correctly.

can you attach your current fsm, memory and tb code once more?

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Re: BRAM Acces to write it from PL and read from PS and compute that data

//FSM//

module FSM_DATA_ADDR_GENERATOR(
input wire SYSCLK,
input wire RESET,
input wire GO,
input wire RESET_SIGNAL,
input wire DONE_SW,
output wire WE,
output wire EN,
output wire OVER,
output wire [9:0]ADDRESS,
output wire[31:0]DATA_IN
);
////////////////////////////////////////////////////////////////////
reg WE_SIG            = 1'b0;
reg EN_SIG            = 1'b0;
reg OVER_SIG          = 1'b0;
reg [9:0]ADDRESS_SIG  = {3'b100,7'b0000000};
reg [31:0]DATA_IN_SIG = 32'h00000000;
reg [1:0]STATE        = 2'b00;
reg [1:0]STOP_FREQ    = 2'b00; 
/////////////////////////////////////////////////////////////////////////
parameter IDLE        = 2'b00;
parameter INCREMENT   = 2'b01;
parameter STOP_STATE  = 2'b10;
////////////////////////////////////////////////////////////////////////
assign WE             = WE_SIG;
assign EN             = EN_SIG;
assign ADDRESS        = ADDRESS_SIG;
assign OVER           = OVER_SIG;
assign DATA_IN        = DATA_IN_SIG;
/////////////////////////////////////////////////////////////////////////
always@(posedge SYSCLK)
 begin
  if(RESET)
   begin
    STATE    <= IDLE;
   end
 else     
  begin
   case(STATE)

IDLE: begin
   if(GO == 1)
    
     STATE   <= INCREMENT;
      
      else
       begin
    if(RESET_SIGNAL == 1)   
  WE_SIG     <= 1'b1;
  OVER_SIG   <= 1'b0;
  EN_SIG     <= 1'b1;
 ADDRESS_SIG <= {3'b100,7'b0000000};
 DATA_IN_SIG <= 32'h00000000;
      STATE  <= IDLE;
    end
    end
       
      
INCREMENT:
begin
 begin
   WE_SIG    <= 1'b0;
  EN_SIG     <= 1'b0;
  OVER_SIG   <= 1'b0;
 ADDRESS_SIG <= ADDRESS_SIG + {7'b0000000,3'b100};
 DATA_IN_SIG <= DATA_IN_SIG + 32'h04040404;
      STATE  <= INCREMENT;
      end     
    if(DONE_SW == 1)
     STATE   <= STOP_STATE;
    
   end

STOP_STATE:
 begin
  begin
   WE_SIG    <= 1'b1;
   EN_SIG    <= 1'b1;
   OVER_SIG  <= 1'b1;
  STOP_FREQ  <= STOP_FREQ + 1;
   STATE     <= STOP_STATE;  
  if(STOP_FREQ == 2'b00)
   begin  
 DATA_IN_SIG <= 32'h0a3d70a3;
  ADDRESS_SIG <= {7'b0000000,3'b101};

  end
  else if(STOP_FREQ == 2'b01)
    begin
     DATA_IN_SIG <= 32'h0e560618;
     ADDRESS_SIG <= {7'b0000000,3'b110};

    end
  if(RESET_SIGNAL == 1)
  
   STATE     <= IDLE;  
  end
  end
  
  
default:
 begin  
   WE_SIG    <= 1'b0;
  EN_SIG     <= 1'b0;
 ADDRESS_SIG <= {3'b100,7'b0000000};
 DATA_IN_SIG <= 32'h00000000;
      STATE  <= IDLE;
 end

 endcase
 end
end 
endmodule



//RAM//

module BRAM_MD
(input wire SYSCLK,
input wire RESET,
input wire WE,
input wire GO,
input wire RESET_SIGNAL,
input wire DONE_SW,
input wire EN,
input wire [9:0]ADDR,
input wire [31:0]DIN,
input wire OVER,
output wire [31:0]DOUT);
//////////////////////////////////////////////////////////////////////////////////////
reg [31:0] ram [1023:0];//2*10 = 1024;
reg [31:0] DOUT_SIG = 32'h00000000;
//reg OVER_SIG            = 1'b0; 
//////////////////////////////////////////////////////////////////////////////////////

assign DOUT = DOUT_SIG;

////////////////////////////////////////////////////////////////////////////////////// 
always @(posedge SYSCLK )
begin

begin
 if (EN == 1) //optional enable
 begin
 if (WE == 1) //write enable
 ram[ADDR] <= DIN;
 if (RESET == 1) //optional reset
 DOUT_SIG <= 32'h00000000;
 else
 DOUT_SIG <= ram[ADDR];
 end
end
end

FSM_DATA_ADDR_GENERATOR F1(.SYSCLK(SYSCLK),
                           .RESET(RESET),
                           .GO(GO),
                          .RESET_SIGNAL(RESET_SIGNAL),
                          .DONE_SW(DONE_SW),
                          .WE(WE),
                          .EN(EN),
                          .OVER(OVER),
                          .ADDRESS(ADDR),
                          .DATA_IN(DIN)
                          );


endmodule

//TB//

module TEST_MOD();
reg SYSCLK;
reg RESET;
reg GO;
reg RESET_SIGNAL;
reg DONE_SW;
wire EN;
wire WE;
wire [9:0]ADDRESS;
wire [31:0]DATA_IN;
wire OVER;
wire [31:0]DOUT;



BRAM_MD B1 (.SYSCLK(SYSCLK),.RESET(RESET),.GO(GO),.RESET_SIGNAL(RESET_SIGNAL),.DONE_SW(DONE_SW),.EN(EN),.WE(WE),.OVER(OVER),.ADDR(ADDRESS),.DIN(DATA_IN),.DOUT(DOUT));


initial
begin
SYSCLK = 1'b0;
end
always
#5 SYSCLK = ~SYSCLK;



initial
 begin
  RESET  = 1'b0;
 #100;
  RESET  = 1'b0;
  #100;
  RESET  = 1'b1; 
  #100;
  RESET  = 1'b0;

end


initial
begin
 GO          = 0;
RESET_SIGNAL = 0;
DONE_SW      = 0;
#405;

GO           = 0;
RESET_SIGNAL = 1;
DONE_SW       = 0;
#405;

GO           = 1;
RESET_SIGNAL = 0;
DONE_SW      = 0;
#405;


 GO          = 0;
RESET_SIGNAL = 0;
DONE_SW      = 1;
#405;

GO           = 0;
RESET_SIGNAL = 1;
DONE_SW        = 0;
#405;

GO           = 1;
RESET_SIGNAL = 0;
DONE_SW        = 0;
#405;

 GO          = 0;
RESET_SIGNAL = 0;
DONE_SW        = 1;
#405;

GO           = 0;
RESET_SIGNAL = 1;
DONE_SW        = 0;
#405;

GO           = 1;
RESET_SIGNAL = 0;
DONE_SW        = 0;
#405;


GO          = 0;
RESET_SIGNAL = 0;
DONE_SW       = 1;
#405;

GO          = 0;
RESET_SIGNAL = 1;
DONE_SW        = 0;
#405;



end

endmodule

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Re: BRAM Acces to write it from PL and read from PS and compute that data

1.) I dont know why memory is showing as x..and what does this line mean " you should 'poll' this line from your software, after you set 'go' to '1'"?

so "DONE" is like an acknowledgement from FSM to say that it is complete...its not an input..

2.)One more thing...after the controlling of FSM through AXI gpio...HOW DO I GIVE THOSE signals GO,reset,and done....should i use ..physical Switches on FPGA...or should i Assign those values of GO,RESET and done through "SDK" or does it work internally!!! need this clarity!!!

THANKS @ronnywebers 

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