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8,699 Views
Registered: ‎07-11-2010

BRAM with AXI read port and regular write port

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Hello all,

 

I have a circuit that can do a basic write to a simple dual-port memory, using the simple dual-port's native interface. This works well and I'm happy with it - for various reasons I chose not to use a FIFO here.

 

I would like to connect this to my Microblaze processor, and  I'm wondering how to best go about that. Here are the options I thought of, I'm hoping someone can point me in the right direction:

 

1. External slave connection + custom APIF design.

This would involve me creating a custom peripheral with a simple dual-port within, and an AXI4 slave interface, connected through the external shim on the Microblaze. I would prefer to not do this if I can...

 

2. Using the AXI BRAM Controller IP available in EDK, and described in Xilinx DS777 - http://www.xilinx.com/support/documentation/ip_documentation/axi_bram_ctrl/v1_03_a/ds777_axi_bram_ctrl.pdf

This is intriguing, but I've never used it... Will this give me read control over a BRAM using AXI? Will I still have the native BRAM PortA/PortB for something else to write to the BRAM? If not, what is this IP actually for?

 

Any help on this would be really appreciated!!!

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Xilinx Employee
Xilinx Employee
11,962 Views
Registered: ‎07-30-2007

Re: BRAM with AXI read port and regular write port

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Regarding (2.): Yes, the AXI BRAM controller in EDK has two ports that connect to the dual port bram_block.  It can also be configured so that the AXI read and write channels arbitrate for one bram_block port leaving the other port available.

 

It sounds like this is what you want. See the datasheet for more information.

 

I hope this helps,

Dylan

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4 Replies
Xilinx Employee
Xilinx Employee
11,963 Views
Registered: ‎07-30-2007

Re: BRAM with AXI read port and regular write port

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Regarding (2.): Yes, the AXI BRAM controller in EDK has two ports that connect to the dual port bram_block.  It can also be configured so that the AXI read and write channels arbitrate for one bram_block port leaving the other port available.

 

It sounds like this is what you want. See the datasheet for more information.

 

I hope this helps,

Dylan

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8,672 Views
Registered: ‎07-11-2010

Re: BRAM with AXI read port and regular write port

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Dylan,

 

Thanks for your suggestion - for some reason the AutoMailer only notified me today that there was a reply - I did just as you said and the system is working.

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Observer mohanavels
Observer
8,249 Views
Registered: ‎07-22-2011

Re: BRAM with AXI read port and regular write port

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Hi,

 

im also facing now same problem what you have faced earlier.

 

now i want to use BRAM controller IP with microblaze in EDK to controll the dual port RAM read/write access in ISE.  but when i add the BRAM controller in EDK while generate netlist in EDK im facing the Error:

 

ERROR:EDK:4197 - SIGNAL:
   axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Dout -
   multiple drivers found:
   PORT:BRAM_Dout_A -
   C:\Xilinx\14.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\d
   ata\bram_block_v2_1_0.mpd line 89!
   PORT:BRAM_WrData_A -
   C:\Xilinx\14.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_bram_ctrl_v1_03_
   a\data\axi_bram_ctrl_v2_1_0.mpd line 168!
ERROR:EDK:4197 - SIGNAL:
   axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Dout -
   multiple drivers found:
   PORT:BRAM_Dout_B -
   C:\Xilinx\14.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\d
   ata\bram_block_v2_1_0.mpd line 96!
   PORT:BRAM_WrData_B -
   C:\Xilinx\14.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_bram_ctrl_v1_03_
   a\data\axi_bram_ctrl_v2_1_0.mpd line 175!

Running UPDATE Tcl procedures for OPTION SIMGEN_SYSLEVEL_UPDATE_PROC...
make: *** [simulation/behavioral/system_setup.tcl] Error 1
Done!

 

plz help me in this problem

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Contributor
Contributor
7,980 Views
Registered: ‎07-20-2012

Re: BRAM with AXI read port and regular write port

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This sounds very much like what I'm struggling with at the moment.   I have a custom pcore (axi slave) hanging off the AXI bus.

I added a BRAM_CTRL ip  (from the catalog)  which automatically brings a BRAM ip when added to the Microblaze system . I connected the BRAM_CTRL ip as a slave on the AXI bus.

 

I  want my custom pcore to drive Port B of the Block RAM. And the microblaze can share access using PORT A .  

 

Method 1 )   I disconnect  the BLOCK_RAM port B  from the BRAM_CTRL block so I can drive the ports direct from the custom pcore.

I make the custom pcore ports external and BRAM port B ports external.

When I try to interconnect the ports I  select the  port in the connected port column but  in the pull down list of available connections some target ports show up and some do not  ??

 

Method 2 )

 

Leave  both ports A and B connected to the BRAM_CTRL ip  and then make the BRAM_CTRL ip  PORT B ports external. I connect these to the external ports of the custom pcore. 

When I do this the connection list under External ports shows they are connected but the ports list under the connected ports tab for the BRAM_CTRL ip were removed as I connected each port ??

 There is no indication the connections are made in the graphical view ?

 

 

Any help on this would be appreciated.  Please let me know which method above is correct ( if any )  and  how I can resolve this issue.   I have attached the mhs file for each method.

 

 Thanks very much.

 

 

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