08-27-2014 01:18 AM
Is there any way to access DDR memory from PL bypassing the inbuilt DDR controller? I want to instantiate DDR controller provided as soft IP in PL and access the external DDR memory through it. The flow is something like this:
PS-------------->DDR controller instantiated in PL-------------------------->External DDR memory
(Ignoring in between AXI ports and interconnects for simplicity)
Is it possible to do so? If yes, please give me some hints to do so.
If it is not possible to do so, I want to understand why Xilinx provided DDR controller soft IP which can be instantiated in PL. Please help me in clarifying these.
08-27-2014 01:20 AM - edited 08-27-2014 01:21 AM
It is possible please refer UG586 for MIG generation in PL, to interface it to PS you can enable AXI interface in MIG and make use of AXI interconnect IPs
Hope this helps
08-27-2014 10:57 PM
08-30-2014 01:18 AM
08-31-2014 08:35 PM
Thanks for the response. Unfortunately this solution does not serve my purpose. I have a ZebBoard with ZYNQ XC7Z020-CLG484 interfaced with 512 M DDR3 external memory. This memory module is connected to PS via existing DDR3 controller in PS. I want to access this existing DDR memory using my own DDR controller in PL section. For this, I want to bypass existing DDR controller in PS. Is it possible to do so? Or, is it possible to configure the existing DDR controller in such a way that it blindly processes the incoming commands without re-ordering/. My intention here is to use my customized logic in DDR controller to access the memory.
What I understand from MIG is that it helps to generate memory interface and controller in FPGA logic. My intention here is not to generate another memory interface in PL section of Zynq. I need a transparent access to existing DDR here.
Is it possible in Zynq? If not, what will be the right platform which can serve my purpose.
Thanks a lot...
08-31-2014 09:10 PM
>> I want to access this existing DDR memory using my own DDR controller in PL section.
could you explain why you are trying to do this?
>> For this, I want to bypass existing DDR controller in PS. Is it possible to do so?
Probably not. DDR controller is a quite a complex block which ends with a DDR PHY. It would be quite difficult to take over all the blocks in there.
>> Or, is it possible to configure the existing DDR controller in such a way that it blindly processes the incoming commands without re-ordering.
This might be possible to some degree. Read chapter 10 of the Zynq TRM (ug585). You maybe able to configure the subblocks of the DDR controller to give up some of the scheduling/re-ordering etc but it would be quite complicated to do so. Not to mention you would be leaving a lot of throughput on the table and increase the latency quite bit. I am really curious why you would want to do this.
>> If not, what will be the right platform which can serve my purpose.
If the purpose was known, we could come up with an answer. If you really want to implement your controller, you can design a new board and generate a MIG which is PHY only and do everything yourself (at least that used to be possible in the past. I am not sure if the current MIG allows that anymore but it's certainly doable as you only need the DDR IO which is on the FPGA)
08-31-2014 11:34 PM
You will have a phy only option in PL - MIG but I do not think you can byapss controller in PS DDR, so I am not sure your requirement can be achieved.
If you could explain us the reason behind your concept of PL controlller + PS phy then one of us will try to give more clues for alternatives
09-01-2014 12:40 AM
Thanks for your explanation. It really helps .The reason why I want to have my own controller is to implement my own logic for arbitration and things like that.
The whole purpose is to build customized DDR controller in PL logic of Zynq in ZedBoard. However it looks like it is not quite possible to do so as it involves DDR PHY and stuffs like that.
One more thing that I noticed in XPS is that, in Zynq graphical view, it is possible to disable the DDR controller using configuration window. What happens when I disable it? Is it going to be disconnected from memory port on processing system/ARM? In that case it is isolated and neither ARM nor PL can access external DDR because by disabling DDR controller we are disabling the entire path. Am I coerrect?
Again, thanks for your time..
09-01-2014 01:04 AM
09-02-2014 04:15 AM
Thanks for exaplaining the reason, but to implement your design concept you need to have the DDR connected to PL section where you can use MIG phy only RTLs and have your own controller
As per disabling DDR I hope your understanding is correct.