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Visitor xkokes01
Visitor
5,463 Views
Registered: ‎07-08-2016

Clocking Wizard - Dynamic clock reconfig - Zynq AXI lite

Hi,

 

I need to use the clocking wizard IP and dynamic reconfig feature. I have checked the dynamic reconfig in clocking options and then I have run connection automation in vivado block designer. Now I can see the offset address of this component (0x43C0000) in Address Editor.

 

But when I try to read or write to the address by Xil_Out32 or Xil_In32 in the SDK, the program stops.

Another components like GPIO AXI, AXI Timer, Partial Reconfiguration Controller, ... works fine.

 

Do you know where is the problem with the clocking wizard IP?

 

Thanks

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3 Replies
Moderator
Moderator
5,367 Views
Registered: ‎07-31-2012

Re: Clocking Wizard - Dynamic clock reconfig - Zynq AXI lite

Hi,

 

Are you sure that the address shown is of clock wiz IP?

There shouldn't be issue with checking dynamic clock reconfig option.

 

Let see if I can provide you the same example application.

 

Regards

Praveen


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Visitor xkokes01
Visitor
5,330 Views
Registered: ‎07-08-2016

Re: Clocking Wizard - Dynamic clock reconfig - Zynq AXI lite

It's solved. I'm silly. The Vivado connection automation didn't connect "s_axi_aresetn" pin.

I haven't noticed that.
When I connect it manualy it works fine.
Thanks

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1,338 Views
Registered: ‎07-27-2017

Re: Clocking Wizard - Dynamic clock reconfig - Zynq AXI lite

Hello i am also struggeling to get the dynamic clock reconfiguration running.

 

I think i did everything right on the vivado side, but not sure if my sdk code is valid. Could you provide an example c code or a complete example project?

 

Here is the relevant part of my code:

 

//Clock Config Setup XPAR_CLK_WIZ_0_BASEADDR
#define CLKOUT0_DIV 40
#define CLKOUT0_FRAC 0
#define CLKOUT1_DIV 12
#define CLKOUT1_FRAC 12

 

u32 *CLK_WZD = (u32 *)XPAR_CLK_WIZ_0_BASEADDR;

//try to read the wizzard status
//u32 statusreg = *(CLK_WZD + 4);

//Configure CLOCKDIV0
*(CLK_WZD + 520/*0x208*/) = (0 << 18) + ((CLKOUT0_FRAC & 255) << 8) + (CLKOUT0_DIV & 255);


//statusreg = *(CLK_WZD + 4);

//Configure CLOCKDIV1
//*(CLK_WZD + 532/*0x214*/) = (0 << 18) + ((CLKOUT1_FRAC & 255) << 8) + (CLKOUT1_DIV & 255);

//set LOAD and SEN bits in Clock Config Register
*(CLK_WZD + 604/*0x25C*/) = 0x7;

//reset LOAD and SEN bits in Clock Config Register
*(CLK_WZD + 604/*0x25C*/) = 0x2;

 

Thanks and Best Regards

 

Felix 

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