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Visitor spu_rds
Visitor
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Registered: ‎01-09-2019

Configuring AXI quad SPI v3.2 LogicCORE IP as standard Master for low frequency(500 KHz)

Hi, I have implemented  the "AXI Quad SPI" as standard Master (SPI clock 5MHz) on a Virtex 7 . When I have set the frequency ration to '2' , "ext_spi_clk" and "s_axi_clk" to "10MHz" , transaction width  to  '8'. I am able to get the proper SPI bus clock output.

When i tried to reduce the SPI clock frequency to 1MHz by setting the frequency ration to '16 X 1' , "ext_spi_clk" and "s_axi_clk" to "16MHz" , transaction width  to  '8' and enabled the FIFO with depth '256'. I am not able to get the proper SPI bus clock output I'm getting only 2 clock cycles instead of 8 clock cycles.

Please help me out in configuring SPI for low frequencies between 500 KHz to 1 MHz.

I have attached the pic of block diagram, SPI configuration and clocking wizard configuration.

Thanks & Regards,

Spurthi

SPI_1MHz_BD.png
SPI_1MHZ_CLKWIZ_CNFG.png
SPI_1MHZ_SPI_CNFG.png
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