04-23-2017 08:29 PM - edited 04-23-2017 08:50 PM
Software: Vivado 2016.2
HW Platform: XC7Z035-XXXX
I have a 512Mbyte DDR3 connected to PL I/O of Zynq. Bit file generation is OK.
In Vivado, if this DDR (MIG IP) is connected to PS7 block through axi_interconnect IP 2.1, only lower 256Mbyte is addressable. Is this limitation of axi_interconnect IP? There are other IPs sharing this axI_interconnect IP but there is room for 512Mbyte range.
Then I enabled M_AXI_GP1 on PS7 then try to connect MIG IP's AXI slave directly to M_AXI_GP1, to try to bypass limitation of axi_interconnect. But block diagram editor does not allow me to connect. Is this because it must go through axi_interconnect?
Pls advice. Tks
04-23-2017 10:06 PM
@wtneo in the address editor how big is the range assigned to mig ddr?
the reason you can't connect ps7 to mig directly is probably because ps7 is axi3 and mig is axi4 so you need a protocol translator which the interconnect has as a feature.
04-23-2017 10:18 PM
My main objective is to connect MIG directly to PS7 is so that I can access full 512Mbyte. Is axi_interconnect the restriction why I could only access 256Mbyte?
05-09-2017 12:17 AM
M_AXI_GP1 address range is 8000_0000 to BFFF_FFFF, make sure that the MIG address range is in this range.
And also see the address editor for any conflicts.