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64 Views
Registered: ‎11-19-2013

Cortex-A9 MMU and cache relationship

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Hi,

    I want to simplify the boot code of PS, because i don't use any OS on the chip, just bare-run. Then i want to disable the MMU. But i find cache and MMU are related in cortex-a9 technical reference, is it safe to use cache while disable MMU?

Thanks .

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Voyager
Voyager
35 Views
Registered: ‎04-13-2015

Re: Cortex-A9 MMU and cache relationship

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huangj852010@163.com

The MMU & cache work in pair.  Enabling the cache / no MMU will not allow you to set the type of caching; i.e. memory, device, strongly ordered; the MMU table provides this info.  More importantly, if the cache could operate without the MMU, how could accesses to the peripherals registers region be un-cached (that's the MMU job).

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Voyager
Voyager
36 Views
Registered: ‎04-13-2015

Re: Cortex-A9 MMU and cache relationship

Jump to solution

huangj852010@163.com

The MMU & cache work in pair.  Enabling the cache / no MMU will not allow you to set the type of caching; i.e. memory, device, strongly ordered; the MMU table provides this info.  More importantly, if the cache could operate without the MMU, how could accesses to the peripherals registers region be un-cached (that's the MMU job).

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