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Adventurer
Adventurer
7,953 Views
Registered: ‎02-13-2016

Create Clock Constraint - VGA Interface

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Hello,

 

I am implementing a VGA interface on ZYBO Zynq 7000 for 1600x900 60 Hz screen, with a pixel_clk of 106.47MHz.

 

I am using Vivado 2014.2, with .xdc constraint file.

 

Please make your illustration as simple as possible.

PORT (
clk: IN STD_LOGIC; --50MHz in our board
pixel_clk: BUFFER STD_LOGIC;
-- Remaining Code

ARCHITECTURE vga OF vga IS
PROCESS (clk)
 BEGIN
 IF (clk'EVENT AND clk='1') THEN
 pixel_clk <= NOT pixel_clk;
 END IF;
 END PROCESS;

 

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Xilinx Employee
Xilinx Employee
13,336 Views
Registered: ‎07-31-2012

Re: Create Clock Constraint - VGA Interface

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Hi @asobeih,

Answering your pending questions.

Another thing, what is the difference between the following three .xdc commands for clock constraints? And what are the circumstances to use each of them?

set_property PACKAGE_PIN L16 [get_ports clk]
[A] This assigns the top modules IO signals in your design to the actual FPGA IO on the hardware chip.
-----------------------------------------------------------------------------------------------
set_property IOSTANDARD LVCMOS33 [get_ports clk]
[A] This assigns the IO standard for the above same pin/signal/IO.
-------------------------------------------------------------------------------------------
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports clk]

[A] This creates the clock constraints for the clock port. This ensures that all the paths driven by this clock meet setup and hold slack so that the design meets timing.

In case you still have queries, please check the tcl command reference guide and you will have all the answers.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
7 Replies
Xilinx Employee
Xilinx Employee
7,928 Views
Registered: ‎07-31-2012

Re: Create Clock Constraint - VGA Interface

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Is there a question here?
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Adventurer
Adventurer
7,908 Views
Registered: ‎02-13-2016

Re: Create Clock Constraint - VGA Interface

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@athandr

Sorry, I have overwritten the question while writing down the details by mistake.

 

Anyway, I want to know the steps to how to create the required clocks for my design using Vivado (considering the given details)

 

I already tried to use the Constraints Wizard and Edit Timing Constraints, but I really could not manage to do it right, and I cannot recognize the right pattern to create these clocks (like Should I create the pixel_clk as a Generated Clock or as a normal clock?

 

I just need to understand the while mechanism in the simplest manner.

 

Thanks

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Xilinx Employee
Xilinx Employee
7,905 Views
Registered: ‎07-31-2012

Re: Create Clock Constraint - VGA Interface

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Any clock is fine as far as it has a good SI i.e low jitter. However I guess your question is regarding the timining constraints. What you should be worried about here is, "Is my design meeting timing for this reference clock". For this

1) You can either write a create_clock constraint and then analyze the paths analyzed by this in the timing tool
2) Or when you want to re-constrain the timing after a specific registers, you can write a create_generated_clock constraint, which does the analysis accordingly too.

You can refer the Vivado timing user guide to further understand these.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Adventurer
Adventurer
7,898 Views
Registered: ‎02-13-2016

Re: Create Clock Constraint - VGA Interface

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Okay, I will refer to it and come back for any further inquiries.

 

Another thing, what is the difference between the following three .xdc commands for clock constraints? And what are the circumstances to use each of them?

 

set_property PACKAGE_PIN L16 [get_ports clk]

-----------------------------------------------------------------------------------------------
set_property IOSTANDARD LVCMOS33 [get_ports clk]

-------------------------------------------------------------------------------------------
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports clk]

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Adventurer
Adventurer
7,883 Views
Registered: ‎02-13-2016

Re: Create Clock Constraint - VGA Interface

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@athandr

 

Okay, I will refer to it and come back for any further inquiries.

 

Another thing, what is the difference between the following three .xdc commands for clock constraints? And what are the circumstances to use each of them?

 

set_property PACKAGE_PIN L16 [get_ports clk]

-----------------------------------------------------------------------------------------------
set_property IOSTANDARD LVCMOS33 [get_ports clk]

-------------------------------------------------------------------------------------------
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports clk]

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Voyager
Voyager
7,866 Views
Registered: ‎04-21-2014

Re: Create Clock Constraint - VGA Interface

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In DocNav, take a look at UG935, which is a tutorial.


@asobeih wrote:

Okay, I will refer to it and come back for any further inquiries.

 

Another thing, what is the difference between the following three .xdc commands for clock constraints? And what are the circumstances to use each of them?

 

set_property PACKAGE_PIN L16 [get_ports clk]

-----------------------------------------------------------------------------------------------
set_property IOSTANDARD LVCMOS33 [get_ports clk]

-------------------------------------------------------------------------------------------
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports clk]


 

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Xilinx Employee
Xilinx Employee
13,337 Views
Registered: ‎07-31-2012

Re: Create Clock Constraint - VGA Interface

Jump to solution
Hi @asobeih,

Answering your pending questions.

Another thing, what is the difference between the following three .xdc commands for clock constraints? And what are the circumstances to use each of them?

set_property PACKAGE_PIN L16 [get_ports clk]
[A] This assigns the top modules IO signals in your design to the actual FPGA IO on the hardware chip.
-----------------------------------------------------------------------------------------------
set_property IOSTANDARD LVCMOS33 [get_ports clk]
[A] This assigns the IO standard for the above same pin/signal/IO.
-------------------------------------------------------------------------------------------
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports clk]

[A] This creates the clock constraints for the clock port. This ensures that all the paths driven by this clock meet setup and hold slack so that the design meets timing.

In case you still have queries, please check the tcl command reference guide and you will have all the answers.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.