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Observer maxdz8
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Registered: ‎01-08-2018

Create and package new IP (AXIS-L): what is 'number of registers"?

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If I click on the label, the popup reads:

Defines the number of registers to be added in generated template HDL, NUM_REG is supported only for AXI-Lite Slave interfaces.

Those end creating a few variables named slv_regN and associated logic to write to them, commented as "memory mapped register select and write logic generation". A second block of code towards the end "memory mapped register select and read logic generation" copies the value back to reg_data_out.

 

Those look quite convenient but:

  1. As for mapping write (to device) ops, why is there a default: case... copying the values in themselves? Wouldn't this be the same as not doing anything?
  2. What if I have a peripheral taking 8 32-bit values in but gives only 1 32-bit value out?
  3. If I compare to xapp1204, dds_config.v, there are not such things there. But xapp1204 does quite a different thing.
  4. Can you suggest some other content adeguate to a beginner?

My current approach would involve writing some assignments after the // Add user logic here line, compile the whole thing to SDK, run (I'm using a Zynq) the device though the driver and pull out with xil_printf or maybe the debugger. That sounds like a lot of work, there must be a better way. What am I missing?

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Scholar hbucher
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Registered: ‎03-22-2016

Re: Create and package new IP (AXIS-L): what is 'number of registers"?

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@maxdz8

 

1. Yes, that is the default behavior. This is just a template.

 

2. This cannot be enforced. In/out behavior has to be known by the client.

 

3. It is a different implementation. The protocol only dictates the signals, not behavior, what you do with them. 

 

4. It is not much but I did a video on the subject a while ago

 

http://www.vitorian.com/x1/archives/594

 

Hope this helps.

 

UPDATE: As per #1 I did not realize exactly what you meant. 

Check out here why defaults in switch cases are important:

https://www.researchgate.net/post/Latch_inference_in_case_block

 

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Scholar hbucher
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Registered: ‎03-22-2016

Re: Create and package new IP (AXIS-L): what is 'number of registers"?

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@maxdz8

 

1. Yes, that is the default behavior. This is just a template.

 

2. This cannot be enforced. In/out behavior has to be known by the client.

 

3. It is a different implementation. The protocol only dictates the signals, not behavior, what you do with them. 

 

4. It is not much but I did a video on the subject a while ago

 

http://www.vitorian.com/x1/archives/594

 

Hope this helps.

 

UPDATE: As per #1 I did not realize exactly what you meant. 

Check out here why defaults in switch cases are important:

https://www.researchgate.net/post/Latch_inference_in_case_block

 

vitorian.com --- We do this for fun. Always give kudos. Accept as solution if your question was answered.
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Observer maxdz8
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Registered: ‎01-08-2018

Re: Create and package new IP (AXIS-L): what is 'number of registers"?

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Thank you @hbucher, I guess I definitely learned something.

 

The regs are only part of the picture, if I think at it as an address space it indeed makes more sense.

 

At ~ 6:00 you propose to add logic to max values right in LN225-230. It wasn't my understanding I were supposed to put my logic there but it does indeed help.

 

Yet my design requires all the regs to be set before running and my understanding is AXI does not deal with this. I have been considering the possibilities WRT the suggestion and I'll think I'll add my own set of signals.  It is my understanding if I call a wire ap_start Vivado will glue it to driver for me so I'm going to try it out and see what happens.

 

Edit: thank you for the update. I wasn't expecting it to be such a problematic issue. I understand some of those words so I'll just take it as pattern to be respected for the inference to pick up.

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Scholar hbucher
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Registered: ‎03-22-2016

Re: Create and package new IP (AXIS-L): what is 'number of registers"?

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@maxdz8  If I remember well the template IP has an initial block where you can set your parameters.  There is also a reset block. 

Is that what you mean?

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Observer maxdz8
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Registered: ‎01-08-2018

Re: Create and package new IP (AXIS-L): what is 'number of registers"?

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I don't think so @hbucher, I'll rephrase.

 

As far as I understand of the AXI template, it transacts 32 bit values. Apparently those 32 bit values are 'strobed' - somehow provided in byte chunks. The AXI boilerplate memorizes those bits to the slv_regN regs. This is where AXI ends, in the sense its job is done.

 

My design needs all 8 integers to be set. Otherwise we would OFC evaluate random bits. Therefore, I need a all data is good, you're green to go signal. It is my understanding this should be called ap_start.

 

I'm considering I might also use slv_reg19 to start the processing. I'm pretty sure I've seen that happen on some SPI devices. I'm not very much into this possibility.

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Scholar hbucher
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Registered: ‎03-22-2016

Re: Create and package new IP (AXIS-L): what is 'number of registers"?

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@maxdz8  Pre-conditions are enforced by semantics. The client has to obey the rules. 

Even HLS does not have a valid flag inside to check if the registers were initialized.

It is understood that once ap_start is raised, your component state has been correctly initialized. 

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