09-17-2014 04:18 AM
Currently, I build a system on Nexys 4 using vivado 2014.2. It includes Microblaze, EMC for PSRAM, AXI_DMA and some other gpio. Before adding AXI_DMA, everything is OK, but after adding AXI_DMA, I received a critical warning like this when I run implemeation.
[BD 41-1265] Different peripherals </microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem> and </microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem> are mapped into related masters </microblaze_0/Instruction> and </microblaze_0/Data> at the same offset
For auto assign address, both of them are the same. However, I don't know why Vivado shows me that errors. It's OK for ignoring it or I did something wrong. To be honest, I just use automation tool of vivado to connect those block together and a little bit scare of when see a critical warning.
Another critical warning is timing violated when adding AXI DMA. I have no idea for those critical warning.
Here I attach a timing report.
I wonder that those critical warning influence my design or not. Even if I got two critical warnings, the bitstream file is generated successfully.
Thank you very much.
09-17-2014 04:20 AM
09-27-2014 06:53 PM
i have the same programe,can you tell me how to solve this problem.
09-28-2014 05:14 AM
I didn't solve this problem yet. Actually, I didn't care it and kept doing my job.
my system works well and I hope it's not a major problem on the way I've been working in my project.
09-29-2014 08:51 AM