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Observer lucianocapasso
Observer
5,002 Views
Registered: ‎05-31-2013

Custom IP as master of the AXI bus for BURST data transfers

Hi everybody,

 

I'm trying to implement a custom IP able to manage as master the AXI4 bus. I have created my IP via the "Create or Import Peripheral" wizard, selecting the "AXI4: burst capable high thoughput memory mapped interface" radio button. I have attached to this message the user_logic.vhd file generated by the wizard. Such file contains some template processes to implement master transactions on the AXI4 bus.

 

From line 327, it is explained how to start a single write to an IP on the AXI bus:

 

  1. write 0x02 to the control register (that is the "Write" flag)
  2. write the target address to the address register (0xC0000000 in my case)
  3. write valid byte lane value to the be register. Then it says "this value must be aligned with ip2bus address" but I actually don't know what does it mean. Any suggestion? I tried several byte enable values: 0xFF, 0xF and 0x2
  4. write 0x0004 to the length register (4 bytes, i.e. one int word)
  5. write 0x0a to the go register, this will start the master write operation

Well,the bus gives an error and I don't know why. As you can see in the attached snapshot of a simulation of my program, I did exactly all it is described in the above points.

 

Is there anybody going to give to me any suggestion? Maybe I wrote wrong values in the Byte Enable register?

 

Thanks in advance.

 

Regards,

 

Luciano

 

 

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Simulation_labelled.jpg
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4 Replies
Observer lucianocapasso
Observer
4,950 Views
Registered: ‎05-31-2013

Re: Custom IP as master of the AXI bus for BURST data transfers

No idea?

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Observer psouthard
Observer
4,850 Views
Registered: ‎02-05-2008

Re: Custom IP as master of the AXI bus for BURST data transfers

Have you considered using the AXI BFM to simulate your design?  It's quite helpful.

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Moderator
Moderator
4,803 Views
Registered: ‎08-25-2009

Re: Custom IP as master of the AXI bus for BURST data transfers

I would also consider using AXI BFM to simulate the custom IP and make sure it does not violate the axi protocol. ds824 has the steps to do so. Hope it helps.
"Don't forget to reply, kudo and accept as solution."
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Explorer
Explorer
4,717 Views
Registered: ‎05-11-2012

Re: Custom IP as master of the AXI bus for BURST data transfers

I am having a similar error.  I appear to get the error when I attempt to write less than 32 bytes out...my Custom IP uses a 128 bit data width.

 

http://forums.xilinx.com/t5/Embedded-Processors-and/AXI-Master-Burst-Transfer-Errors/td-p/357885

 

I traced the error reported by mst_reg[1] to come from the WR_CNTRL of the AXI_Master_Burst module of the Custom IP as the sig_tlast_err_ovrrun error, but I don't know what this means...Have you figured out what was causing your error?

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