07-03-2013 04:38 AM
I'm trying to implement a custom IP able to manage as master the AXI4 bus. I have created my IP via the "Create or Import Peripheral" wizard, selecting the "AXI4: burst capable high thoughput memory mapped interface" radio button. I have attached to this message the user_logic.vhd file generated by the wizard. Such file contains some template processes to implement master transactions on the AXI4 bus.
From line 327, it is explained how to start a single write to an IP on the AXI bus:
Well,the bus gives an error and I don't know why. As you can see in the attached snapshot of a simulation of my program, I did exactly all it is described in the above points.
Is there anybody going to give to me any suggestion? Maybe I wrote wrong values in the Byte Enable register?
Thanks in advance.
08-06-2013 04:49 PM
Have you considered using the AXI BFM to simulate your design? It's quite helpful.
08-27-2013 02:33 AM
09-14-2013 11:24 AM
I am having a similar error. I appear to get the error when I attempt to write less than 32 bytes out...my Custom IP uses a 128 bit data width.
I traced the error reported by mst_reg to come from the WR_CNTRL of the AXI_Master_Burst module of the Custom IP as the sig_tlast_err_ovrrun error, but I don't know what this means...Have you figured out what was causing your error?