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Observer vijji148
Observer
2,264 Views
Registered: ‎07-06-2016

Custom axi4 full master with MIG

Hi,

I'm using Kintex7 FPGA Board(xc7k70t - fbg484). I designed axi4 full master (with burst transactions increment type) custom IP and created Vivado block design with axi4 full master custom IP, axi Bram and related peripherals. Tested using ILA debugging working fine. I added MIG instead of Bram in Vivado block design but, write transaction itself is not working (I used same axi4 full master as used for Bram) . I connected MIG with axi4 full master directly without interconnect as shown in below.

mig.PNG

Please help me to find issues with the following diagram.

Any help would be appreciated.

 

Thanks in advance.

 

Regards,

Vijaya 

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2 Replies
Teacher muzaffer
Teacher
2,223 Views
Registered: ‎03-31-2012

Re: Custom axi4 full master with MIG

@vijji148 the MIG has a very detailed simulation model so you can simulate your axi master and the mig together. Have you done this?

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Observer vijji148
Observer
2,187 Views
Registered: ‎07-06-2016

Re: Custom axi4 full master with MIG

Thank you @muzaffer for your response.

 

I resolved the issue. The design was correct and the problem is with my axi full master verilog code. I modified the code and its working with the same design.

 

Regards,

Vijaya

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