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Visitor onofognol
Visitor
252 Views
Registered: ‎06-03-2018

Custom cache between Microblaze and MIG

I followed the tutorial for "getting started with microblaze" for the Nexys4DDR.  After verifying its correct operation, I set out to do my actual task: a custom cache between the Microblaze and the MIG.

I first generated a custom IP as an AXI4-Lite interface peripheral.  Initially, I left the code exactly as-is and connected it with some difficulty between the microblaze M_AXI_DC interface and the smartconnect generated as a part of the connection automation process.  This also worked without incident.

Finally, I added in some simple code to my IP as a test: any data that appears on the s0_axi_awdata port is negated.  After repackaging my IP, I incorporated it into my block design again, and began to experience many errors at the implementation stage.  The errors were all variations of the following:

 

[Opt 31-67] Problem: A LUT3 cell in the design is missing a connection on input pin I1, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: bd_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/w_sreg/m_vector_i[1025]_i_1.

I also tried recreating the Microblaze without a cache, and attaching my IP as a peripheral to the MIG through a smc interconnect.  This failed with the same errors.

 

Please advise as to how to create a custom block between the Microblaze and the MIG.  Ideally I would have access to read and write data and addresses.  This is the basic configuration I was hoping for:

MicroBlaze <----> Custom AXI Peripheral IP <----> MIG

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3 Replies
Visitor onofognol
Visitor
247 Views
Registered: ‎06-03-2018

Re: Custom cache between Microblaze and MIG

As some additional information, here is my current full block diagram setup:

Screenshot at 2018-12-03 02_08_35.png

 

 

 

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Xilinx Employee
Xilinx Employee
179 Views
Registered: ‎02-01-2008

Re: Custom cache between Microblaze and MIG

My first thought is that your core is not forwarding all the necessary axi4 signals. Or maybe a property is missing.

First thing to try is to open the synth design, and use schem viewer to see the signals between faultMaker and axi_smc.

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Visitor onofognol
Visitor
58 Views
Registered: ‎06-03-2018

Re: Custom cache between Microblaze and MIG

As a followup, I also tried a few other things unsuccessfully.

 

After running connection automation on the tutorial design, I expanded all the signals.  I recorded all which pins on the smartconnect were connected to the MIG.  I replicated all these signals, and connected them manually.  The synthesis failed catastrophically.

 

I also tried to edit the connections made by the connection automation tool.  I really only need to modify a handful of signals, none of which are control signals.  There does not appear to be a way to do so.

 

Thanks in advance for any help you can provide

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