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Newbie cvasantha
Newbie
151 Views
Registered: ‎04-24-2019

DDR Memory Base Address in ZYNQ

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Hi, 

I am using JTAG to AXI ip and wants to do some DDR Read & Write transactions. So i am using HP slave port from ZYNQ PS. In address editior getting the base address as 0x00000000. But in hdf file or linker script file base address of DDR was showing as 0x00100000. If i want to use RAM how to use  that one and what will be the address. when i am writing to 0x0 or 0x100000 using JTAG to axi master but in SDK some garbage values it was showing. 

Processor is executing the code from that location and i am also trying to wrote some data to that locations. When i am using HP interface to access DDR and RAM what will be the locations. Is there any changes that i need to do. In SDK i want to check wether my written data is updated or not. Am i going in correct way. Please help me.

Thanks in advance..

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1 Solution

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Xilinx Employee
Xilinx Employee
103 Views
Registered: ‎09-01-2014

Re: DDR Memory Base Address in ZYNQ

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It depends on the address filtering setting.
Please check the register setting mentioned in the Address mapping section.
And if the initial setting is used, 0x0 is OCM and it ‘s a reset vector which should not be changed.
If you want to access DDR, starting from 0x10_0000.
3 Replies
Xilinx Employee
Xilinx Employee
136 Views
Registered: ‎09-01-2014

Re: DDR Memory Base Address in ZYNQ

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Because that area is used by OCM. please check Table 29-1: Initial OCM/DDR Address Map
http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
and OCM is relocated booting from Linux, then you can see DDR is from address 0x0.
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Newbie cvasantha
Newbie
116 Views
Registered: ‎04-24-2019

Re: DDR Memory Base Address in ZYNQ

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Thanks for reply.

But i am writing the bare metal code. If i create JTAG transcations for writing to 0x0 location and able to read the data which i have written but not able to see the expected result in SDK.

 

What is the base address for DDR if i am using HP slave interface?

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Xilinx Employee
Xilinx Employee
104 Views
Registered: ‎09-01-2014

Re: DDR Memory Base Address in ZYNQ

Jump to solution
It depends on the address filtering setting.
Please check the register setting mentioned in the Address mapping section.
And if the initial setting is used, 0x0 is OCM and it ‘s a reset vector which should not be changed.
If you want to access DDR, starting from 0x10_0000.