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Visitor prashanthim
Visitor
1,281 Views
Registered: ‎09-20-2016

DDR4 to FIFO Via MIG controllers in zynq ultra scale + mpsoc

Hi,

I am working on ZYNQ ULTRA SCALE + MPSOC.

I have to control such a very high speed data to PS DDR4 with out any data loss.

 

I designed  a block diagram in vivado 16.3,That is in IP level.

input to axi stream fifo ,then fifo to dma controller, and then dma to DDR4 in PL side.

 

but i am not sure that is it works perfectly or not..

 

i need some support or suggestions as soon as possible.

 

the main concept is high speed data need to store in DDR4.

 

 

Thank You.

 

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2 Replies
Scholar u4223374
Scholar
1,271 Views
Registered: ‎04-26-2015

Re: DDR4 to FIFO Via MIG controllers in zynq ultra scale + mpsoc

That should work perfectly. Unless it's (a) failing timing, or (b) giving obvious evidence that it's not working, then it's pretty safe to assume that it is working.

 

The obvious test is to feed it some known data. For example, on an 8-bit input just send in sequential 0, 1, 2, 3, 4, 5 ... 255 inputs. Then look through the RAM and verify that no values were missed or doubled-up.

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Visitor prashanthim
Visitor
681 Views
Registered: ‎09-20-2016

Re: DDR4 to FIFO Via MIG controllers in zynq ultra scale + mpsoc

is it possible to simulate this block design..?

 

i am getting error while simulating this.  the error is zynq ultra scale + mpsoc device does not support simulation..

if there is chance, plz let me know.

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